S71GL064A08 SPANSION [SPANSION], S71GL064A08 Datasheet - Page 21

• Manufacturer Part Number: S71GL064A08
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Device Bus Operations
Legend: L = Logic Low = V
Address, A
Notes:
1.
2.
3.
4.
February 8, 2005 S71GL064A_00_A2
Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection
and Unprotection” section.
If WP# = V
sector devices). If WP# = V
method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the factory (The Secured
Silicon Sector may be factory protected depending on version ordered.)
D
IN
or D
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Sector Group Protect
(Note 2)
Sector Group
Unprotect
(Note 2)
Temporary Sector
Group Unprotect
Requirements for Reading Array Data
OUT
IN
IL
= Address In, D
Operation
as required by command sequence, data polling, or sector protect algorithm (see
, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot
This section describes the requirements and use of the device bus operations, which are ini-
tiated through the internal command register. The command register itself does not occupy
any addressable memory location. The register is a latch used to store the commands, along
with the address and data information needed to execute the command. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
they require, and the resulting output. The following subsections describe each of these op-
erations in further detail.
To read array data from the outputs, the system must drive the CE# and OE# pins to V
CE# is the power control and selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up, or after a hard-
ware reset. This ensures that no spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to obtain array data. Standard mi-
croprocessor read cycles that assert valid addresses on the device address inputs produce
IH
IL
, the first or last sector, or the two outer boot sectors will be protected or unprotected as determined by the
A d v a n c e
, H = Logic High = V
IN
V
0.3 V
CE#
CC
= Data In, D
X
X
L
L
L
L
L
L
±
OE#
H
H
X
H
X
H
H
X
L
Table 1. Device Bus Operations
Table 1
WE#
OUT
H
X
H
X
X
L
L
L
L
I n f o r m a t i o n
S71GL064A based MCPs
IH
= Data Out
lists the device bus operations, the inputs and control levels
, V
RESET#
V
0.3 V
ID
V
V
V
CC
H
H
H
H
L
ID
ID
ID
= 11.5–12.5 V, V
±
(Note 3)
(Note 3)
WP#
H
H
H
X
X
X
X
IH
.
ACC
V
HH
X
X
H
X
X
X
X
X
HH
= 11.5–12.5 V, X = Don’t Care, SA = Sector
A3=L, A2=L,
A3=L, A2=L,
A1=H, A0=L
A1=H, A0=L
SA, A6 =L,
SA, A6=H,
Addresses
(Note 1)
Figure
A
A
A
A
X
X
X
IN
IN
IN
IN
2).
DQ0–DQ15
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
High-Z
High-Z
High-Z
D
OUT
IL
.
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