S71GL064A08 SPANSION [SPANSION], S71GL064A08 Datasheet - Page 99

• Manufacturer Part Number: S71GL064A08
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

February 8, 2005 S71GL064A_00_A2
Temperature Compensated Refresh (for 64Mb)
Deep Sleep Mode
Reduced Memory Size (for 32M and 16M)
Other Mode Register Settings (for 64M)
tings for the PASR operation are defined in
ZZ# is active low, only the portion of the array that is set in the register is re-
freshed. The data in the remainder of the array will be lost. The PASR operation
mode is only available during standby time (ZZ# low) and once ZZ# is returned
high, the device resumes full array refresh. All future PASR cycles will use the
contents of the Mode Register that has been previously set. To change the ad-
dress space of the PASR mode, the Mode Register must be reset using the
previously defined procedures. For PASR to be activated, the register bit, A4 must
be set to a one (1) value, “PASR Enabled”. If this is the case, PASR will be acti-
vated 10 µs after ZZ# is brought low. If the A4 register bit is set equal to zero
(0), PASR will not be activated.
In this mode of operation, the internal refresh rate can be optimized for the op-
eration temperature used and this can then lower standby current. The DRAM
array in the PSRAM must be refreshed internally on a regular basis. At higher
temperatures, the DRAM cell must be refreshed more often than at lower tem-
peratures. By setting the temperature of operation in the Mode Register, this
refresh rate can be optimized to yield the lowest standby current at the given op-
erating temperature. There are four different temperature settings that can be
programmed in to the pSRAM. These are defined in
In this mode of operation, the internal refresh is turned off and all data integrity
of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 reg-
ister bit set to a zero (0), “Deep Sleep Enabled”. If this is the case, Deep Sleep
will be entered 10 µs after ZZ# is brought low. The device will remain in this mode
as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep
Sleep will not be activated.
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb
device. The mode and array size are determined by the settings in the VA register.
The VA register is set according to the following timings and the bit settings in
the table “Address Patterns for RMS”. The RMS mode is enabled at the time of
ZZ transitioning high and the mode remains active until the register is updated.
To return to the full 32Mb address space, the VA register must be reset using the
previously defined procedures. While operating in the RMS mode, the unselected
portion of the array may not be used.
The Page Mode operation can also be enabled and disabled using the Mode Reg-
ister. Register bit A7 controls the operation of Page Mode and setting this bit to a
one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode
operation is disabled.
A d v a n c e
I n f o r m a t i o n
S71GL064A based MCPs
Table
25. In this PASR mode, when
Figure
33.
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