GS880E32T-100 GSI [GSI Technology], GS880E32T-100 Datasheet - Page 16
GS880E32T-100
Manufacturer Part Number
GS880E32T-100
Description
512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS880E32T-100.pdf
(25 pages)
- Current page: 16 of 25
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Write Cycle Timing
Rev: 1.11 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQ
A
B
ADSC
ADSP
A
–DQ
A
ADV
0
–B
GW
–A
BW
CK
E
E
E
G
D
D
n
1
2
3
Hi-Z
Single Write
tS tH
tS tH
tS tH
tS tH
tS tH
WR1
tS tH
ADV must be inactive for ADSP Write
tS tH
tS tH
tS tH
tS tH
tS tH
WR1
WR1
D1
A
E
2
and E
WR2
t
KH
3
Write specified byte for 2
only sampled with ADSP or ADSC
t
KL
WR2
WR2
Burst Write
D2
16/25
A
tKC
D2
ADSP is blocked by E inactive
E
B
1
masks ADSP
D2
A
and all bytes for 2
C
GS880E18/32/36T-11/11.5/100/80/66
D2
D
Write
ADSC initiated write
WR3
WR3
WR3
D3
B
, 2c& 2
A
Deselected with E
© 2000, Giga Semiconductor, Inc.
D
Deselected
2
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