GS880E32T-100 GSI [GSI Technology], GS880E32T-100 Datasheet - Page 20
GS880E32T-100
Manufacturer Part Number
GS880E32T-100
Description
512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS880E32T-100.pdf
(25 pages)
- Current page: 20 of 25
- Download datasheet (853Kb)
Rev: 1.11 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipelined DCD Read-Write Cycle Timing
DQ
B
A
A
ADSC
ADSP
–DQ
A
0
–A
ADV
–B
GW
BW
CK
E
E
E
n
D
G
D
1
2
3
Hi-Z
tS tH
tS
tS
tS
tS tH
RD1
tH
tH
tH
Single Read
tS tH
tS tH
tS
tKQ
tOE
E
Q1
tKH
2
tOHZ
and E
A
tKL
20/25
3
only sampled with ADSP and ADSC
tH
Single Write
tKC
tS tH
tS tH
tS tH
D1A
WR1
WR1
RD2
ADSC initiated read
ADSP is blocked by E
GS880E18/32/36T-11/11.5/100/80/66
E
1
masks ADSP
Burst Read
Q2
A
1
© 2000, Giga Semiconductor, Inc.
inactive
Deselected with E
Q2
B
Q2c
Preliminary
3
Q2
D
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