GS880E32T-100 GSI [GSI Technology], GS880E32T-100 Datasheet - Page 5

• Manufacturer Part Number: GS880E32T-100
• Description: 512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

TQFP Pin Description
Rev: 1.11 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
18, 19, 22, 23, 24, 25, 28, 29
4, 11, 20, 27, 54, 61, 70, 77
13, 12, 9, 8, 7, 6, 3, 2
47, 48, 49, 50, 43
51, 52, 53, 56, 57
16, 38, 39, 42, 66
Pin Location
25, 28, 29, 30
15, 41, 65, 91
51, 80, 1, 30
51, 80, 1, 30
1, 2, 3, 6, 7
75, 78, 79,
37, 36
93, 94
95, 96
95, 96
98, 92
84, 85
80
87
89
88
97
86
83
64
14
31
ADSP, ADSC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Symbol
A
B
B
A
E
A9
V
A1
B1
C1
D1
C9
A1
B1
ADV
LBO
2
GW
V
V
BW
C
A
NC
NC
A
NC
CK
NC
0
1
ZZ
FT
DDQ
–A
E
, DQ
G
, A
–DQ
–DQ
–DQ
–DQ
, DQ
–DQ
–DQ
, B
, B
, E
DD
SS
18
2
17
1
B
D
3
B9
A8
B8
C8
D8
D9
A9
B9
,
5/25
Typ
I/O
I/O
I/O
—
—
—
—
e
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
Address Strobe (Processor, Cache Controller); active low
Address field LSBs and Address Counter preset Inputs
Byte Write Enable for DQ
Burst address counter advance enable; active low
Global Write Enable—Writes all bytes; active low
Byte Write—Writes all enabled bytes; active low
Data Input and Output pins (x32, x36 Version)
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
GS880E18/32/36T-11/11.5/100/80/66
Sleep mode control; active high
Clock Input Signal; active high
Data Input and Output pins
Data Input and Output pins
Output driver power supply
No Connect (x32 Version)
No Connect (x18 Version)
Output Enable; active low
Chip Enable; active high
Chip Enable; active low
I/O and Core Ground
Core power supply
Address Inputs
Address Inputs
Description
C
No Connect.
No Connect
, DQ
Version)
A
D
, DQ
Data I/Os; active low (x32, x36
© 2000, Giga Semiconductor, Inc.
B
Data I/Os; active low
Preliminary