AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet
AMD-762JLC
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AMD-762JLC Summary of contents
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... AMD-762™ System Controller Publication # 24416 Rev: C Issue Date: December 2001 Data Sheet ...
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... AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo and combinations thereof, AMD Athlon, AMD-760, AMD-761, AMD-762, AMD-766, and AMD-768 are trademarks of Advanced Micro Devices, Inc. Alpha is a trademark of Digital Equipment Corporation. ...
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... Contents Revision History 1 Features 1.1 AMD Athlon™ System Buses . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Integrated Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 AGP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Functional Operation 2.1 Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Out of Order, Split Transaction . . . . . . . . . . . . . . . . . . . 7 2.1.2 Point-to-Point, Source Synchronized . . . . . . . . . . . . . . . 8 2.1.3 Push-Pull Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Memory Interface 2.2.1 DRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 ...
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... AMD-762™ System Controller Data Sheet 2.4 Accelerated Graphics Port (AGP) 2.5 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.6.1 Full-On (C0 2.6.2 Halt (C1 2.6.3 Throttling with STPCLK# Assertion . . . . . . . . . . . . . . . 27 2.6.4 Power-On Suspend (S1 2.6.5 Suspend to RAM (S3 Test 3.1 Board (Three-State) Test Mode . . . . . . . . . . . . . . . . . . . . . . . 35 3.1.1 Board Test Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 NAND Tree Test Mode 3 ...
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... Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table of Contents Preliminary Information AMD-762™ System Controller Data Sheet Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . . 62 AGP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Bus Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 x86 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 General References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Websites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 71 73 ...
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... AMD-762™ System Controller Data Sheet vi Preliminary Information 24416C—December 2001 Table of Contents ...
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... Figure 25. List of Figures Preliminary Information AMD-762™ System Controller Data Sheet AMD-760MPX™ System Block Diagram (66-MHz PCI AMD-760MP™ Chipset System Block Diagram (33-MHz PCI) 6 Push-Pull Transmission Line Example . . . . . . . . . . . . . . . . . . . 9 Dummy Load with External Compensation Resistors . . . . . . . 9 AMD-762™ System Controller Connection to DDR DIMMs . 12 DRAM Refresh Timing ...
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... AMD-762™ System Controller Data Sheet viii Preliminary Information 24416C—December 2001 List of Figures ...
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... List of Tables Preliminary Information Total Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AMD Athlon Processor System Bus NAND Tree Ordering . . . 38 AMD-762 System Controller AGP NAND Tree Ordering . . . . . 41 AMD-762 System Controller DDR NAND Tree Ordering . . . . 42 AMD-762 System Controller PCI NAND Tree Ordering . . . . . 44 Clocking Options in PLL Bypass Test Mode . . . . . . . . . . . . . . . 45 Clock Output Test Mode Options ...
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... AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( Signal Descriptions Table Definitions . . . . . . . . . . . . . . . . . . . . 81 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Initialization Pinstrapping ...
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... Revision History Date Rev Added AMD-768 peripheral bus controller throughout as the Southbridge device for the MPX Dec./2001 C chipset. June/2001 B-1 Package name in datasheet corrected from PBGA to CCGA. June/2001 B Initial public release. Nov./2000 A Initial NDA release. Revision History AMD-762™ ...
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... AMD-762™ System Controller Data Sheet xii Preliminary Information 24416C—December 2001 Revision History ...
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... Accelerated Graphics Port (AGP) controller, and Peripheral Component Interconnect (PCI) bus controller. Figure 1 on page 5 shows a block diagram for the AMD-760MPX chipset. Figure 2 on page 6 shows a block diagram for the AMD-760MP chipset. The AMD-762 system controller is designed with the following ...
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... Controller Data Sheet, order# 23167. For a description of the AMD-768 peripheral bus controller, see the AMD-768™ Peripheral Bus Controller Data Sheet, order# 24467. Key features of the AMD-762 system controller are provided in this section. 1.1 AMD Athlon™ System Buses The AMD Athlon system buses have the following features: ...
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... Compliance with PCI Local Bus Specification, Revision 2.2. n Supports up to seven PCI bus masters plus the AMD-766 peripheral bus controller when operating in 33-MHz-only mode two PCI bus masters and the AMD-768 peripheral bus controller when operating in 66/33-MHz PCI mode. n 64-bit interface, compatible with 3.3-V and 5-V PCI I/O ...
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... Power Management The power management features include the following: n Compliance support for both Advanced Configuration and Power Interface (ACPI) and Microsoft management n The AMD-762 system controller supports the following power states: • • 4 Preliminary Information Compliance with Accelerated Graphics Port Interface Specification, Revision 2 ...
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... Refer to Figure 1 for a block diagram of the AMD-760MPX™ chipset with an AMD-768 peripheral bus controller (66-MHz PCI). Refer to Figure 2 on page 6 for a block diagram of the AMD-760MP chipset with the AMD-766 peripheral bus controller (33-MHz PCI). 64-bit data + 8-bit ECC ...
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... SADDOUT System Controller SERR# SBREQ# SBGNT# WSC# DCSTOP# System Management, Reset, Initialize, Interrupts Figure 2. AMD-760MP™ Chipset System Block Diagram (33-MHz PCI) 6 Preliminary Information AMD Athlon™ AMD Athlon Processor Processor System Buses Memory Bus AMD-762™ System Controller 64-bit data + 8-bit ECC ...
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... This section describes the functional operation of the AMD-762™ system controller. 2.1 Processor Interface The two AMD Athlon processor system buses are high- performance, out-of-order, split-transaction buses, each capable of transferring one processor command and one probe response, one chip-set response and one probe request, and one data packet simultaneously ...
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... AMD-762™ System Controller Data Sheet 2.1.2 Point-to-Point, Source Synchronized All of the AMD Athlon system bus signals use a terminated, point-to-point topology—that is, there is one signal connection plus termination on each end of each wire. The terminated point-to-point topology allows the use of incident wave signalling, eliminating most of the time for transmission line reflections ...
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... Separate compensation is performe d for the N and P transistors. The drive strength is changed in small steps when no data is being driven. Refer to Figure Figure 4. Dummy Load with External Compensation Resistors Chapter 2 AMD-762™ System Controller Data Sheet Transmission Line + VTT INP INN Dummy Driver Functional Operation ...
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... SDRAM DIMMs. The AMD-762 system controller memory interface is designed to support registered DDR DIMMs four registered DIMMs can be supported by the AMD-762 system controller. The AMD-762 system controller supports 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit DDR devices. Device widths of x4, x8, and x16 are supported ...
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... MBit (16M banks) 512 MBit ( banks) Note: The maximum address space supported by the AMD-762 system controller is 4 Gbytes. Support of four registered DIMMs is accomplished by the AMD-762 system controller’s eight DDR chip-select pins (CS[7:0]#), which allow DIMMs with two chip selects as illustrated in Figure 5 on page 12 ...
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... AMD-762™ System Controller Connection to DDR DIMMs 2.2.1 DRAM Refresh The AMD-762 system controller keeps track of when each independently. Refresh is only performed on rows that are populated. A concurrent refresh cycle can be executed in parallel with other read and write requests, if there conflict and the command bus is free ...
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... In the case of writes to memory, the AMD-762 system controller must drive DQS such that each edge is centered in the write-data valid window to allow the DDR DRAMs to capture the data on each edge of the strobe. ...
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... Because the system clock is generated by a PLL in the AMD-762 system controller that is already compensated for PVT, the system clock period is independent of PVT. Therefore, the clock period can be assumed constant, and can be used to correlate the PDL values to units of time ...
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... PCI agents are clocked from the system clock generator’s PCI clocks. The desired PCI clocking mode is selected with the AD[15] pinstrap on the AMD-762 system controller. Refer to Chapter 7 on page 81 for details of the AMD-762 system controller’s pinstrapping. The AMD-762 system controller drives the 64-bit PCI bus synchronously with the PCI clock ...
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... PCI bus among itself on behalf of the processors, the Southbridge, and other PCI initiators. The AMD-762 supports up to seven bus grant pins and a dedicated grant pin for the Southbridge when operating in legacy mode. The request/grant pairs used depend on the system configuration supported as described in the following sections ...
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... Southbridge such as described in “Legacy Mode—Single PCI Bus Southbridge” on page 16. When there are no requests for the bus, ownership can default to either processor through the AMD-762 system controller or the last PCI bus master that had bus ownership. This mode is called bus parking and is controlled by the PCI Arbitration Control register (Dev 0:F0, 0x84, bit 0) ...
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... PCI SERR# signal. This action results in the error being reported by the Southbridge. The AMD-762 system controller does not check parity on the PCI bus. The status bit (Dev 0:04h, bit 31) is always 0. 18 ...
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... PCI Top of Memory (Dev 0:F0:0x9C), the AMD-762 system controller accepts the cycle and responds as a PCI target by asserting DEVSEL#. If the address is not within the defined memory region, the AMD-762 system controller ignores the cycle and allows it to complete on the PCI. ...
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... Freedom from the coherency requirements of PCI, which eliminates the latency resulting from cache snooping. n Full PCI 2.2 capability, which enables the AMD-762 system controller to pass programming information from the processor to the graphics adapter Graphics Address Remapping Table (GART). ...
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... Low-priority reads push low-priority writes, meaning that a write request is serviced before a subsequently received read request is serviced. n Low-priority writes can pass low-priority reads, meaning that a write request can be serviced before a previously received read request. Chapter 2 AMD-762™ System Controller Data Sheet Functional Operation 21 ...
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... Southbridge as described in the following sections. 66-MHz PCI Bus The highest performance option supports a 66-MHz primary PCI bus on the AMD-762 system controller, with a 33-MHz secondary PCI bus controlled by an AMD-768 peripheral bus controller’s PCI to PCI bridge. This mode also provides up to two optional slots for 66-MHz peripherals ...
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... Southbridge and the two PCI bus slots in this mode 33-MHz-only card is inserted in one of the 66-MHz PCI slots, then the M66EN signal is deasserted, which causes the AMD-762 system controller to drive 33 MHz on the PCI_66CLK[2:0] pins. The 66-MHz PCI mode is illustrated in Figure 7. ...
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... PCI PLL when operating in 66-MHz mode. This requires the PCI_66CLK[0] output pin to be connected back into the AMD-762 system controller’s PCICLK input for skew control, as shown in Figure 7 on page 23. These PLLs can be bypassed for motherboard testing. Refer to Chapter 3 for further details of PLL bypass testing ...
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... Southbridge. SMM memory remapping is handled by a model-specific register in the AMD Athlon processor. See the AMD Athlon™ BIOS Developers Guide, order# 21656, for more information about the SMM remapping operation ...
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... communicate power-state transitions through the AMD Athlon system bus connect/disconnect protocol and special cycles (masked writes to a defined AMD Athlon system bus address with specific data encoding). In general, the processor initiates a request for a disconnect with a special cycle, and the AMD-762 system controller may or may not actually disconnect the processor with the connect/disconnect protocol ...
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... AMD-762 system controller disconnects the processor and places system memory into self-refresh mode before passing the special cycle to the PCI Bus. If the AMD-762 system controller detects a PCI DMA master transaction that needs a snoop, then the processors are connected, DRAM is taken out of self-refresh mode, and the probe cycle(s) are initiated on the AMD Athlon processor system buses ...
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... STPCLK# assertion and the Stop Grant state. The Southbridge asserts the DCSTOP# signal, which is used by the AMD-762 system controller to gate off internal clock trees for lower power. All power supplies remain on, and the clock synthesizer chip on the motherboard continues to drive all clocks. ...
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... DRAM in self-refresh mode. The DRAM controller initiates self-refresh, then acknowledges to the power management logic. • 6. The AMD-762 system controller issues a Stop Grant special cycle on the PCI bus. 7. The Southbridge detects the Stop Grant special cycle on the PCI bus and asserts the DCSTOP# signal. ...
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... The processors assert their respective PROCRDY signal, which causes the AMD-762 system controller to exit self-refresh and reconnect the AMD Athlon processor system buses. The configuration registers during the S1 state ...
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... DCSTOP#. After entering S3 state with DCSTOP# assertion, the Southbridge asserts the RESET# signal, which causes the AMD-762 system controller to gate off its I/O rings to accommodate the voltages being removed from the AMD Athlon processor system bus, PCI bus, and AGP bus. The AMD-762 system controller core remains powered (2 ...
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... AMD-762™ System Controller Data Sheet 6. The AMD-762 system controller issues a Stop Grant special cycle on the PCI bus. 7. The Southbridge asserts DCSTOP#. The AMD-762 system controller follows the normal DCSTOP# protocol as described in “S1 Sequence” on page 28, including gating most of the internal clocks off. The DDR output clocks (CLKOUT[5:0], CLKOUT[5:0]#) continue running for an additional six clock periods from the assertion of RESET# ...
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... Suspend to RAM System Timing Diagram Example Chapter 2 30– CPU Disconnect 4 Occurs Here Self-Refresh Functional Operation AMD-762™ System Controller Data Sheet 20–50 ms 1.5–2 ms 30–60 ms Running Full Speed Running Full Speed Running Full Speed Running Full Speed 33 ...
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... RESET# pin. Upon exiting the S3 sleep state, BIOS writes the appropriate value to these bits, which causes the AMD-762 system controller to exit self-refresh. The two register bits (STR_Control) are in the DRAM Mode/Status register (Dev 0:F0:0x58). Refer to the AMD-762™ System Controller Software/BIOS Design Guide, order# 24416 for detailed information on these bits ...
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... PLL bypass test • Clock output test Three-state test and NAND tree test can be used to prevent the AMD-762 system controller from driving its pins and to verify connectivity of the AMD-762 system controller to the motherboard. The PLL bypass and clock output test modes are provided primarily for motherboard debug and can be used to verify system clocking and drive slower clocks into the system ...
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... I/O type, which create the following trees: n AMD Athlon system bus NAND tree This tree includes all signals on the AMD Athlon processor system bus. SYSCLK is not included in the NAND tree. The output of this tree is the GNT[0]# pin. The ordering for this NAND tree is shown in Table 2 on page 38 ...
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... NAND tree is shown in Table 4 on page 42. n PCI NAND tree This tree includes PCICLK and PCI bus signals, excluding the RESET# input. The output of this tree is the GNT[2]# pin. The ordering for this NAND tree is shown in Table 5 on page 44. Chapter 3 AMD-762™ System Controller Data Sheet Test 37 ...
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... AMD-762™ System Controller Data Sheet Table 2. AMD Athlon™ Processor System Bus NAND Tree Ordering Input Pin # Ball Name 1 P0_SADDOUT[14]# D-1 2 P0_SYSFILLVAL# J-8 3 P0_SADDOUT[10]# F-5 4 P0_SADDOUT[13]# E-2 5 P0_SADDOUT[07]# E-1 6 P0_SADDOUTCLK# E-3 7 P0_SADDOUT[05]# F-4 8 P0_SADDOUT[09]# F-2 9 P0_SADDOUT[12]# F-1 10 P0_SADDOUT[11]# G-5 11 P0_SADDOUT[08]# F-3 12 P0_SADDOUT[02]# G-1 13 P0_SADDOUT[03]# H-2 14 P0_SADDOUT[04]# G-3 15 P0_SADDOUT[06]# H-4 16 P0_SDATA[54]# H-6 17 P0_SDATA[55]# H-5 18 P0_SDATA[61]# H-7 19 P0_SDATA[50]# J-7 20 P0_SDATA[48]# K-7 21 P0_SDATAOUTCLK[3]# H-1 ...
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... Table 2. AMD Athlon™ Processor System Bus NAND Tree Ordering (Continued) Input Pin # Ball Name 94 P0_SDATA[13]# W-7 95 P0_SDATA[11]# Y-7 96 P0_SADDIN[03]# AA-2 97 P0_SDATAINVALID# AB-1 98 P0_SADDIN[02]# Y-4 99 P0_SADDIN[05]# Y-5 100 P0_SADDIN[11]# Y-6 101 P0_SADDIN[04]# AA-6 102 P0_SADDIN[07]# AA-3 103 P0_SADDIN[06]# AA-4 104 P0_SADDIN[10]# AB-5 105 P0_SADDINCLK# AA-7 106 P0_SADDIN[08]# AA-5 107 P0_SADDIN[09]# AB-3 108 P0_SADDIN[14]# ...
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... AMD-762™ System Controller Data Sheet Table 2. AMD Athlon™ Processor System Bus NAND Tree Ordering (Continued) Input Pin # Ball Name 185 P1_SDATA[24]# AK-14 186 P1_SDATA[30]# AJ-12 187 P1_SDATA[28]# AJ-13 188 P1_SDATA[03]# AD-14 189 P1_SDATA[01]# AJ-14 190 P1_SDATA[07]# AE-13 191 P1_SDATA[00]# AE-14 192 P1_SDATA[05]# AL-14 193 P1_SDATA[09]# AD-15 194 P1_SCHECK[0]# ...
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... Table 3: AMD-762™ System Controller AGP NAND Tree Ordering Order Input Pin Name Ball 1 A_GNT# AD-27 2 SBA[1] AB-25 3 PIPE# AE-29 4 WBF# AC-26 5 SBA[5] AA-25 6 ST[1] AD-28 7 A_REQ# AD-29 8 ST[0] AC-27 9 ST[2] AC-28 10 SBA[7] AA-26 11 A_AD[30] Y-25 12 SBA[3] AB-27 13 RBF# AC-29 14 A_AD[28] Y-26 15 CBE[3]# V-25 16 SBA[2] AA-27 17 SBA[0] AB-29 18 A_AD[26] W-25 19 A_AD[20] U-25 20 A_AD[22] V-26 21 SBA[4] Y-27 22 SBSTB AA-28 Chapter 3 AMD-762™ System Controller Data Sheet ...
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... AMD-762™ System Controller Data Sheet Table 4: AMD-762™ System Controller DDR NAND Tree Ordering Order Input Pin Name Ball 1 MDAT[59] E-29 2 MDAT[63] E-27 3 DQS[7] D-29 4 CLKOUT[5] F-26 5 DCSTOP# G-25 6 MDAT[58] E-28 7 MDAT[62] C-29 8 CLKOUT[2]# F-25 9 MDAT[57] C-27 10 DM[7] C-28 11 CLKOUT[2] E-26 12 CS[6]# D-25 13 MDAT[56] B-28 14 CLKOUT[5]# D-27 15 CS[5]# E-24 16 MDAT[60] B-27 17 CS[1]# E-23 18 MDAT[61] C-26 19 MDAT[51] A-27 20 MDAT[55] C-25 21 CS[7]# E-25 22 ...
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... Table 4: AMD-762™ System Controller DDR NAND Tree Ordering (Continued) Order Input Pin Name Ball 103 MAB[03] E-9 104 MDAT[28] C-7 105 MDAT[24] A-6 106 MAA[04] D-7 107 MDAT[22] A-5 108 MAB[04] E-8 109 MDAT[23] C-6 110 MDAT[19] B-6 111 MDAT[18] A-4 112 MAB[06] D-6 113 DM[2] B-4 114 MAA[06] ...
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... PLL bypass test mode provides a method to clock the Northbridge core logic directly from an external source without the need for the internal PLLs of the AMD-762 system controller. This test mode is sometimes useful for motherboard debug and is required in the three-state and NAND tree test modes ...
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... PLL bypass mode as listed in Table 6 below. Because the AMD-762 system controller internal logic normally uses clocks that are 2x the SYSCLK input and 2x/4x the AGPCLK input, the PLL bypass mode requires that either clocks be driven in this mode, but they can be driven at a much lower frequency for test purposes ...
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... AMD-762™ System Controller Data Sheet Table 7. Clock Output Test Mode Options AD[07:05] SYSCLK PLL Output GNT[5]# Pin 000 1x SYSCLK clock after internal divide by two 001 SYSCLK input 010 Reserved, undefined 011 Reserved, undefined 100 1x SYSCLK output from SYSCLK PLL 101 Reserved, undefined ...
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... Electrical Data 4.1 Absolute Ratings The AMD-762™ system controller is not designed to operate beyond the parameters shown in Table 8. Note: The absolute ratings in Table 8 and associated conditions Table 8. VDD_CORE, A_VDD, K7_VCORE VDD_AGP, VDD_PCI REF_5V V PIN V PIN System Bus V PIN V PIN ...
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... AMD-762™ System Controller Data Sheet 4.2 Operating Ranges The AMD-762 system controller is designed to provide parameters are within the limits defined in Table 9. Table 9. ...
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... DC Characteristics Table 11 shows the DC characteristics for the AMD-762 system controller. Table 12 on page 50 shows DC characteristics for the PCI I/Os. Table 13 on page 51 shows DC characteristics for AGP I/ mode. Table 14 on page 52 shows DC characteristics for AGP I/ and 4x modes. Table 10. ...
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... ATX power supply and therefore is powered up before the 3.3 VDC, and the AMD-762 system controller can tolerate this for up to one second also assumed that the VREF voltages are always powered from the associated power supply voltage and will therefore lag behind that voltage ...
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... Absolute maximum pin capacitance for an AGP-compliant component input (except for CLK) with an exception granted to motherboard-only devices, which could order to accommodate PGA packaging. Generally, this means that com- ponents for expansion boards need to use alternatives to ceramic PGA packaging—that is, PQFP, BGA, etc. Chapter 4 AMD-762™ System Controller Data Sheet Condition Min 0.5 V ...
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... AMD-762™ System Controller Data Sheet Table 14. AGP 2x and 4x Mode DC Specifications* DC Specifications for 2x Mode Only at 3.3-Volt Signalling Symbol Parameter Description V Input Reference Voltage REF I V Pin Input Current REF REF C Input Pin Capacitance IN C Strobe to Data Pin Capacitance Delta IN DC Specifications for Mode at 1.5-Volt Signalling ...
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... Clock Switching Requirements Table 16 contains the switching characteristics of the SYSCLK input to the AMD-762 system controller for 100-MHz processor bus operation. These timings are all measured with respect to the voltage levels indicated by Figure 12 on page 54. Clock skew requirements are shown in Figure 14 on page 56. Table 17 on page 55 contains the switching characteristics of the AGPCLK input for 66-MHz PCI bus operation ...
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... The clock period stability specifies the variance (jitter) allowed between successive periods of the clock inputs measured at appropriate reference voltage. This parameter must be considered as one of the elements of clock skew between the AMD-762 system controller and the system logic. Table 16. SYSCLK Switching Requirements Symbol ...
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... PCICLK Fall Time PCICLK Rise Time PCICLK Period Stability * This table contains preliminary information, which is subject to change. 0.5 VDD_PCI 0.4 VDD_PCI 0.3 VDD_PCI Figure 13. AGPCLK and PCICLK Waveform Chapter 4 AMD-762™ System Controller Data Sheet Preliminary Data Figure Min Max 66 MHz ...
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... DDR Interface Timing Table 19 and Table 20 show the DDR SDRAM interface timings. Figure 15 on page 57 shows DDR clock specifications. The AMD-762 system controller’s DDR DRAM interface complies to JEDEC specifications for 100/133-MHz device timing. Table 19. DDR Clock Switching Characteristics for 100-MHz DDR Operation ...
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... CLKOUTH[5:0] CLKOUTL[5:0]# Figure 15. DDR Clock Specifications Table 21 shows the AMD-762 system controller preliminary timing information. Table 21. AMD-762™ System Controller Preliminary DDR Timing Information* Symbol Parameter Description V (AC) AC Input Low Voltage IL V (AC) AC Input High Voltage IH t ADDR/CMD Setup to CK ...
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... PLL unbuf_CCLK2X unbuf_CCLK Figure 16. AMD-762™ System Controller DDR Interface Outputs Conceptual Block Diagram early_CCLK set clr CCLK2X Clock Buffers set D Q Clock Buffers Q clr set clr set clr Memory Controller Logic set clr CK CK/ ADDR/CMD DQS ...
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DQSdly t ADhld t ADsu CK ADDR/CMD t WPREhld t WPREsu DQS DQ/DM t DQsu Timing parameter symbols defined at controller interface, not at memory device interface. Note: Figure 17. Address/Command and Memory Write Cycle Timing ...
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... Note: All information shown under From Chip I/O Buffers DQ DQS PDL Figure 18. AMD-762™ System Controller DDR Interface Inputs Conceptual Block Diagram 60 Preliminary Information preliminary. Figure 18 shows a block diagram of the AMD-762 system controller DDR interface inputs, and Figure 19 on page 61 shows memory read cycle timing. CCLK ...
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DQS DQ t CKhi CK Read ADDR/CMD DQS DQ Timing parameter symbols defined at controller interface, not at memory device interface (CAS latency = 2 shown unregistered). Note: Figure 19. Memory Read Cycle Timing t (max) QHrd t (min) DQSQrd ...
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... Data Out Figure 20. Setup, Hold, and Valid Delay Timings AGP Interface Timing The 4x AGP interface of the AMD-762 system controller can operate in three modes — 1x, 2x, and 4x, and complies to the AGP specification parameters. The timings for the 1x mode, shown in Table 22 on page 63, are relative to AGPCLK ...
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... Float Delay (Active to Float Turn-on Delay (Float to Active) on Note: * This table contains preliminary information, which is subject to change. 1. These signals are specified with a 10-pF load. Chapter 4 AMD-762™ System Controller Data Sheet Preliminary Data Min Max Input Signal Requirements 5 ...
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... AMD-762™ System Controller Data Sheet Table 23. AGP 2x Mode Timings* Symbol Parameter Description t Receive Strobe Setup Time to AGPCLK RSsu t Receive Strobe Hold Time from AGPCLK RSH t Data Setup Time Relative to Strobe Dsu t Data Hold Time Relative to Strobe Dh t AGPCLK to Transmit Strobe Falling ...
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... This table contains preliminary information, which is subject to change. 1. These specifications refer to the setup and hold times for the strobe set started in the previous cycle. AGPCLK AD Strobe Figure 21. AGP 2x Strobe/Data Turnaround Timings Chapter 4 AMD-762™ System Controller Data Sheet Preliminary Data Min Max Transmitter Output Signals 1 – ...
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... AMD-762™ System Controller Data Sheet AGPCLK AMD-762™ Transmit Data AMD-762 Transmit Strobe AMD-762 Receive Data AMD-762 Receive Strobe Figure 22. AGP 2x Timing Diagram AGPCLK Transmit Strb/Strb# t DVb Transmit Data t DVa Receive Strb/Strb# t DSu Receive Data Figure 23. AGP 4x Timing Diagram 66 Preliminary Information ...
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... Strobe Figure 24. AGP 4x Strobe/Data Turnaround Timing PCI Interface Timings Table 25 on page 68 shows the PCI interface timings. Table 26 shows 66-MHz PCI interface timings. All of the timings are relative to PCLK. Chapter 4 AMD-762™ System Controller Data Sheet t OFFD t OFFS Electrical Data t ONd ...
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... AMD-762™ System Controller Data Sheet Table 25. 33-MHz PCI Interface Timings* Symbol Parameter Description AD[63:0] Setup Time SBREQ#, REQ[6:0]# Setup Time Setup Time for FRAME# STOP TRDY# DEVSEL# IRDY# C/BE[3:0]# WSC# REQ64# ACK64# AD[63:0] Hold Time Hold Time for FRAME# STOP# TRDY# DEVSEL# ...
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... Min Max RESET WSC clks , and 50 pF for t min max. Electrical Data AMD-762™ System Controller Data Sheet Figure Notes ...
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... AMD-762™ System Controller Data Sheet 4.5.4 AMD Athlon™ Processor System Bus Timings Table 27 shows the AMD Athlon processor system bus timings. Table 27. AMD Athlon™ Processor System Bus/AMD-762™ System Controller AC Specification Group Symbol Parameter Description T Output skew with respect to ...
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... Package Specifications Figure 25 on page 72 shows the package specifications for the AMD-762™ system controller. Chapter 5 AMD-762™ System Controller Data Sheet Package Specifications 71 ...
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... AMD-762™ System Controller Data Sheet AMD PACKAGE SYMBOL MIN. MAX. D/E 39.80 40.20 D1/E1 38.10 BSC. --- D2/E2 D3/E3 21.79 A 4.869 5.257 A1 1.688 A2 1.322 b 0.79 e 1.27 BSC COLUMNS 0.15 aaa bbb 0.26 0.005 ccc Figure 25. 949-Pin Ceramic Column Grid Array (CCGA) Package 72 Preliminary Information NOTES: 1. ALL DIMENSIONS ARE SPECIFIED IN MILLIMETER. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1994. ...
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... Pin Designations This chapter includes a pin connection diagram and pin designation tables with pins grouped by function. Chapter 6 AMD-762™ System Controller Data Sheet Pin Designations 73 ...
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... AMD-762™ System Controller Data Sheet NC1 MDAT1 DQS0 B NC28 MDAT5 VDD_CORE DM0 C NC30 NC31 MDAT4 MDAT0 MDAT6 D P0_SADDOUT14# P0_K7_VCORE0 PDL_OUTPUT_TEST DDR_REF VSS E P0_SADDOUT7# P0_SADDOUT13# P0_SADDOUTCLK# VSS NC36 F P0_SADDOUT12# P0_SADDOUT9# P0_SADDOUT8# P0_SADDOUT5# P0_SADDOUT10# G P0_SADDOUT2# P0_K7_VCORE1 P0_SADDOUT4# VSS P0_SADDOUT11# P0_K7_VCORE7 ...
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... P1_SADDINCLK# P1_CONNECT VSS AGPCLK AK P1_SADDIN11# P1_SADDIN10# P1_K7_VCORE7 DEBUG0# ROM_SCK AL P1_SADDIN5# P1_SADDIN4# P1_CLKFWDRST P1_SYSFILLVALID# ROM_SDA Chapter 6 AMD-762™ System Controller Data Sheet DM5 MDAT46 MDAT52 MDAT54 MDAT55 MDAT60 VDD_CORE MDAT43 MDAT49 VDD_CORE MDAT50 MDAT57 DQS5 MDAT47 MDAT53 ...
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... AMD-762™ System Controller Data Sheet Table 28. AMD-762™ System Controller Pin Functional Grouping ( DDR DRAM Name No. Name No. MAA[14] G-18 CS[0]# H-21 MAA[13] G-19 RASB# F-20 MAA[12] F-9 RASA# G-20 MAA[11] H-11 CASB# G-21 MAA[10] F-18 CASA# G-22 MAA[09] G-10 WEB# H-20 MAA[08] G-11 WEA# E-21 MAA[07] G-9 CKEB F-8 MAA[06] G-12 CKEA G-8 MAA[05] E-11 DQS[8] C-16 MAA[04] F-14 DQS[7] C-28 MAA[03] ...
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... Table 29. AMD-762™ System Controller Pin Functional Grouping ( PCI Bus Name No. Name No. AD[63] R-24 AD[17] W-29 AD[62] N-27 AD[16] V-27 AD[61] N-25 AD[15] U-27 AD[60] M-27 AD[14] U-26 AD[59] M-29 AD[13] T-31 AD[58] M-26 AD[12] R-30 AD[57] P-24 AD[11] T-27 AD[56] L-31 AD[10] V-24 AD[55] M-25 AD[09] R-31 AD[54] L-30 AD[08] T-29 AD[53] M-28 AD[07] U-25 AD[52] K-31 AD[06] R-26 AD[51] L-29 AD[05] U-24 AD[50] L-27 AD[04] P-31 AD[49] L-28 AD[03] T-25 AD[48] L-26 AD[02] P-30 AD[47] K-29 AD[01] R-29 AD[46] K-27 AD[00] P-27 AD[45] M-24 CBE[7]# N-31 AD[44] J-27 CBE[6]# N-29 AD[43] L-25 CBE[5]# M-31 AD[42] J-31 CBE[4]# R-25 AD[41] J-29 CBE[3]# Y-24 AD[40] J-30 CBE[2]# W-25 AD[39] J-28 CBE[1]# V-25 AD[38] H-31 CBE[0]# R-27 AD[37] J-26 PCICLK AH-21 AD[36] H-30 DEVSEL# V-28 AD[35] L-24 FRAME# V-31 AD[34] G-31 WSC# H-28 AD[33] K-25 IRDY# V-29 AD[32] F-31 PAR U-31 AD[31] AA-27 PAR64 M-30 AD[30] Y-26 SERR# U-29 AD[29] Y-27 STOP# U-30 AD[28] AA-30 TRDY# V-30 AD[27] Y-30 REQ64# P-26 AD[26] AA-31 ACK64# R-28 AD[25] AA-28 M66EN U-28 AD[24] Y-31 REQ[0]# E-30 AD[23] Y-25 REQ[1]# F-30 AD[22] W-27 REQ[2]# H-25 AD[21] Y-29 REQ[3]# ...
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... AMD-762™ System Controller Data Sheet Table 30. AMD-762™ System Controller Pin Functional Grouping ( Connects Name No. Name NC0 A-29 P0_CLKFWDRST NC1 A-3 P0_CONNECT NC2 AH-23 P0_PROCRDY NC4 AA-29 P0_SYSCLK NC6 AA-8 P0_SADDIN[02]# NC8 AC-8 P0_SADDIN[03]# NC9 AD-18 P0_SADDIN[04]# NC10 AD-21 P0_SADDIN[05]# NC11 AC-7 P0_SADDIN[06]# NC12 AD-9 P0_SADDIN[07]# NC13 AE-20 P0_SADDIN[08]# ...
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... Table 31. AMD-762™ System Controller Pin Functional Grouping ( Processor 1 AMD Athlon™ System Bus Name No. Name P1_CLKFWDRST AL-19 P1_SDATA[07]# P1_CONNECT AJ-19 P1_SDATA[08]# P1_PROCRDY AE-19 P1_SDATA[09]# P1_SADDIN[02]# AG-17 P1_SDATA[10]# P1_SADDIN[03]# AH-18 P1_SDATA[11]# P1_SADDIN[04]# AL-18 P1_SDATA[12]# P1_SADDIN[05]# AL-17 P1_SDATA[13]# P1_SADDIN[06]# AF-17 P1_SDATA[14]# P1_SADDIN[07]# AG-16 P1_SDATA[15]# P1_SADDIN[08]# AG-18 P1_SDATA[16]# P1_SADDIN[09]# ...
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... AMD-762™ System Controller Data Sheet Table 32. AMD-762™ System Controller Pin Functional Grouping ( VDD Name No. Name No. VDD_CORE AA-11 VDD_CORE M-22 VDD_CORE AA-13 VDD_CORE N-11 VDD_CORE AA-15 VDD_CORE N-13 VDD_CORE AA-17 VDD_CORE N-15 VDD_CORE AA-19 VDD_CORE N-17 VDD_CORE B-10 VDD_CORE N-19 VDD_CORE B-13 VDD_CORE N-21 VDD_CORE B-16 VDD_CORE P-12 VDD_CORE B-19 VDD_CORE P-14 VDD_CORE B-22 VDD_CORE P-16 VDD_CORE B-25 VDD_CORE P-18 VDD_CORE ...
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... Signal Descriptions Table 34 on page 82 contains a description of the AMD-762™ system controller signals. Table 33 describes the terms used in the signal description table. The signals are organized within the following functional groups: • • • • • • • ...
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... SADDIN[14:2]# channel on each edge of SADDINCLK#. AMD Athlon Processor System Bus Connect System Address In Clock SADDINCLK# is the single-ended source-synchronous clock for the SADDIN[14:2]# bus, driven by the AMD-762 system controller. Each clock edge is used to transfer probe and SADDINCLK# O data movement commands to the processor. ...
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... SDATAOUTCLK[3:0]#. SCHECK[7:0]# are floated by RESET#. Check bits for write data are driven by the processor and check bits for read data are driven by the system controller. The AMD-762 system controller drives the previous data value between transfers to prevent floating inputs. AMD Athlon Processor System Bus Processor Data Channel The SDATA[63:0]# transfer data between the processor and system ...
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... The FRAME# pin is asserted by the AMD-762 system controller to indicate the beginning FRAME# STS of a bus transaction. FRAME# is sampled by the AMD-762 PCI target controller when an external bus master is performing a transaction on the PCI bus. PCI Bus Grant As the PCI bus arbiter, the AMD-762 system controller asserts one of these device-specific bus grant signals off the rising clock edge to indicate to an initiator that it has been granted control of the PCI bus the next time the bus is idle ...
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... Type PCI Initiator Ready The AMD-762™ system controller asserts this signal during PCI transactions to indicate B that write data is valid ready to receive read data sampled by the AMD-762 IRDY# system controller during memory transactions by external bus masters to DRAM. STS This pin is also optionally used in test modes as described in Table 36 on page 98, and in Chapter 3 ...
Page 98
... AGP A_SERR# pin assertion errors to error reporting logic on the AMD-766 peripheral bus controller. PCI Stop target, the STOP# signal is asserted by the AMD-762 PCI target logic to initiate a STOP# STS target disconnect, ending the current transfer master, the AMD-762 system controller ends the current transfer when it samples the STOP# signal asserted ...
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... PCI-to-DRAM write transaction is complete. It indicates that an APIC interrupt message can be sent. This signal is used only in configurations where an I/O APIC is installed. WSC# is driven asserted on the rising edge of PCICLK to indicate to the AMD-766™ peripheral bus controller that all probes due to PCI DMA (direct memory access) are B complete ...
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... DRAMs. (The DM pins provide additional strobes when accessing a x4 DIMM.) During reads, the DDR DRAMs source the DQS strobes aligned with MDAT and are used within the AMD-762 system controller to capture read data. (The DM pins are used to receive the DQS signals from the DDR DRAMs when accessing a x4 DIMM.) MDAT[63:0] are floated when neither the AMD-762 system controller nor the memory are driving the bus ...
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... AGP/APCI Clock AGPCLK I AGPCLK receives a 66-MHz clock from the system clock generator. AGPCLK is used by the AMD-762™ system controller logic in the AGP clock domain. Chapter 7 AMD-762™ System Controller Data Sheet Description AGP/PCI Signals Signal Descriptions ...
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... B The AMD-762 system controller asserts this signal during APCI transactions to indicate that A_IRDY# STS write data is valid ready to receive read data sampled by the AMD-762 system controller during transactions by the AGP master. APCI Bus Parity B PAR is used to generate and check for even parity across the AAD[31:00] and A_C/BE[3:]# A_PAR pins ...
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... This signal indicates that the AGP master’s input buffer is full, and that it cannot accept RBF# I more read data. When this signal is asserted by the AGP master, the AMD-762 system controller does not attempt to return previously requested low-priority read data. AGP Write Buffer Full ...
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... Test Mode Enable TEST# I The TEST# pin is used by AMD for internal chip testing also used to enter NAND tree and three-state test modes for motherboard manufacturing test, as described in Chapter 3. Debug These pins are reserved for general-purpose debug. DEBUG[0]# is used for device scan VSS/ testing ...
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... SIP parameters are required that are different than those supplied by the AMD-762™ system controller. This pin must be pulled Low when using the internal SIP ROM table on the AMD-762 system controller or pulled High to use the external ROM. ...
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... I 10: Far dual slot A 11: Farthest possible slot A See the AMD Athlon System Bus Design Guide, order# 22666, for details of the bus length assumptions used in the bus timing calculations. The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88). ...
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... These pins define the clock multiplier for CPU 1, and are generated by the CPU. They are used internally to create the frequency ID (FID) value, which is used in the generation of SIP values sent to the AMD Athlon™ processor during initialization. The table below lists the clock multipliers for each FID value. ...
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... Farthest possible slot A For details of the bus length assumptions used in the bus timing calculations, see the AMD Athlon™ System Bus Design Guide, order# 22666. The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88). Bypass_PLLs (For Test Only) If this pin is pulled High, PLL bypass mode is enabled when TEST# is asserted ...
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... These pins define the clock multiplier for CPU 0, and are generated by the CPU. They are used internally to create the frequency ID (FID) value, which is used in the generation of SIP values sent to the AMD Athlon™ processor during initialization. The table below lists the clock multipliers for each FID value. ...
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... PCI bus PAR (parity) pin 7.3 Pin States at Reset The AMD-762 system controller default pin states are defined in Table 37 on page 99. These are listed for all output and bidirectional pins in the power-on reset state (reset) as well as the ACPI S1 and S3 power management states. Refer to “Power Management” ...
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... Parked signals maintain their previous value Park Z Park Park Z Park Z AMD-762™ system controller asserts per PCI 64-bit Park Z protocol. Park Active Z Can be disabled via configuration register. Active Z Can be disabled via configuration register. Active Z Can be disabled via configuration register ...
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... AMD-762™ System Controller Data Sheet Table 37. Reset Pin States (Continued) Pin Name RESET# State S1 State S3 State MDAT[63:0] Z MECC[7:0] Z CASA# 1 CASB# 1 CLKOUT[5:0] Active CLKOUT[5:0]# Active RASA# 1 RASB# 1 WEA# 1 WEB# 1 A_AD[31:00] Z A_C/BE[3:0]# Z A_DEVSEL# Z A_FRAME# Z A_GNT# 1 A_IRDY# Z A_PAR Z A_STOP# Z A_TRDY# Z ADSTB[1:0] Z ADSTB[1:0]# Z SBSTB ...
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... combination of the elements below. Table 38 shows valid combinations of elements. Contact your AMD representative for detailed ordering information. AMD-762 Table 38. AMD-762JLC Note: Chapter Case Temperature ...
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... AMD-762™ System Controller Data Sheet 102 Preliminary Information Ordering Information 24416C—December 2001 Chapter 8 ...
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... Reserved Bits and Signals—Signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. These bits and signals are reserved by AMD for future implementations. When software reads registers with reserved bits, the reserved bits must be masked. When software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register ...
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... AMD-762™ System Controller Data Sheet n Addressing—Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. n Abbreviations—The following notation is used for bits and bytes: • • • See Table 40 for more abbreviations. n Little-Endian Convention—The byte with the address xx ...
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... Meaning h Hexadecimal K Kilo- Kilobyte M Mega- Mbit Megabit Megabyte MHz Megahertz m Milli- ms Millisecond mW Milliwatt Micro- A Microampere F Microfarad H Microhenry s Microsecond V Microvolt n nano- nA nanoampere nF nanofarad nH nanohenry ns nanosecond ohm Ohm p pico- pA picoampere pF picofarad pH picohenry ps picosecond s Second V Volt W Watt AMD-762™ System Controller Data Sheet 105 ...
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... AMD-762™ System Controller Data Sheet Table 40 contains the definitions of acronyms used in this document. Table 40. Abbreviation CCGA DIMM DRAM EPROM GART HSTL JEDEC 106 Preliminary Information Acronyms Meaning AAT AGP Address Translator ACK Acknowledge ACPI Advanced Configuration and Power Interface AGP ...
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... Physical Page Address PT Page Tables PTE Page Table Entries RAM Random Access Memory ROM Read Only Memory SBA Sideband Address Synchronous Direct Random Access Memory SIP Serial Initialization Packet System Management Bus SMC SDRAM Memory Controller AMD-762™ System Controller Data Sheet 107 ...
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... AMD-762™ System Controller Data Sheet Table 40. Abbreviation SRAM SROM 108 Preliminary Information Acronyms (Continued) Meaning SPD Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory TTL Transistor Transistor Logic VAS Virtual Address Space ...
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... General References Computer Architecture, John L. Hennessy and David A. Patterson, Morgan Kaufman Publishers, San Mateo, CA, 1990. Websites Visit the AMD website for documentation of AMD products. Other websites of interest include the following: n JEDEC home page—www.jedec.org n IEEE home page—www.computer.org n AGP Forum—www.agpforum.org Conventions, Abbreviations, and References AMD-762™ ...
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... AMD-762™ System Controller Data Sheet 110 Preliminary Information Conventions, Abbreviations, and References 24416C—December 2001 ...