AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 26

• Manufacturer Part Number: AMD-762JLC
• Description: System Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD-762™ System Controller Data Sheet
2.3
14
PCI Bus Controller
Because the propagation delay of an individual buffer internal
to the AMD-762 system controller is a function of Process,
Voltage and Temperature (PVT), a mechanism is required to
compensate for these three variables. As mentioned above, the
delay value is known, but the number of buffers that provides
this delay value is not known for a given PVT point. The
calibration mechanism provides this piece of information. The
mechanism used is a simple measurement of how many buffer
delays are required to equal the system clock period. Because
the system clock is generated by a PLL in the AMD-762 system
controller that is already compensated for PVT, the system
clock period is independent of PVT. Therefore, the clock period
can be assumed to be a constant, and can be used to correlate
the PDL values to units of time.
The calibration is automatically performed once after reset and
once after self-refresh exit (before acknowledging self-refresh
exit), and the resultant value is transferred to each PDL.
Recalibration can be initiated via software. The AMD-762 system
controller also has a mode that enables periodic autocalibration.
The AMD-762 system controller supports both 32-bit and 64-bit
PCI agents on a cycle-by-cycle basis as defined by the PCI bus
specification. The AMD-762 system controller asserts the
REQ64# pin during reset to allow 64-bit devices to detect that
the host bridge supports the full 64-bit data width. All 64-bit
transactions from these bus masters are then negotiated with
the PCI bus REQ64#/ACK64# protocol. The address space is still
32-bits maximum when operating with 64-bit transactions.
The AMD-762 system controller supports two PCI clock speed
options as follows:
n 66/33-MHz mode that supports a 66-MHz Southbridge and
two 66-MHz PCI bus slots or on-board chips. In this mode,
the AMD-762 system controller provides the clocks for the
Southbridge and the two optional PCI bus agents. If any of
these devices are 33 MHz only (the M66EN pin is Low), then
the AMD-762 system controller automatically drives 33 MHz
on the PCI_66CLK[2:0] pins during reset.
Preliminary Information
Functional Operation
24416C—December 2001
Chapter 2