AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 72

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AMD-762JLC

Manufacturer Part Number
AMD-762JLC
Description
System Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
AMD-762™ System Controller Data Sheet
DDR Read Timing
Figure 18.
60
From Chip I/O
DQ
DQS
Buffers
AMD-762™ System Controller DDR Interface Inputs Conceptual Block Diagram
Note: All information shown under
PDL
preliminary. Figure 18 shows a block diagram of the
AMD-762 system controller DDR interface inputs, and
Figure 19 on page 61 shows memory read cycle timing.
Preliminary Information
Electrical Data
From PLL
D
D
set
set
clr
clr
Q
Q
Q
Q
CCLK
Memory Controller Logic
DDR Read Timing is
24416C—December 2001
.
Chapter 4

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