AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 64

• Manufacturer Part Number: AMD-762JLC
• Description: System Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD-762™ System Controller Data Sheet
Table 14.
52
DC Specifications for 2x Mode Only at 3.3-Volt Signalling
V
I
C
DC Specifications for 2x or 4x Mode at 1.5-Volt Signalling
V
I
C
Notes:
REF
REF
REF
REF
IN
IN
C
C
Symbol
Symbol
IN
IN
*This table contains preliminary information, which is subject to change.
1. AGP allows differential input receivers to achieve the tighter timing tolerances needed for 133 Mbytes/s. Nominal value of V
2. Although a differential input buffer is not a required implementation, it is recommended especially at higher data transfer rates
3. Capacitance specifications refer only to pin capacitance on the AGP-compliant components used on the AGP interface.
4. Delta C
V
and maximum values. The value of V
nominal V
AGP and PCI specifications. As in other AGP specifications, note that the V
component supply.
where there is less timing margin. All designs regardless of implementation style must meet all other specifications. Component
designs requiring a reference are required to adhere to the V
(A common reference circuit is not applicable to add-in card designs, because V
ated data pins. This delta only applies between signal groups and their associated strobes: AD_STB1, AD_STB1#=>AD[31::16], and
C/BE[3::2]; AD_STB0, AD_STB0#=>AD[15::00], and C/BE[1::0]#; SB_STB, SB_STB#=>SBA[7::0]. (Complementary strobes apply to
4x mode only.)
DDQ
for 3.3-V signalling and 0.5-V
IN
Input Reference Voltage
V
Input Pin Capacitance
Strobe to Data Pin Capacitance Delta
Input Reference Voltage
V
Input Pin Capacitance
Strobe to Data Pin Capacitance Delta 2x Mode
is required to restrict timing variations resulting from differences in input pin capacitance between the strobe and associ-
AGP 2x and 4x Mode DC Specifications*
REF
REF
DDQ
Pin Input Current
Pin Input Current
Parameter Description
Parameter Description
(3.3 V), V
REF
is 1.32 V
DDQ
REF
for 1.5-V signalling. V
2.5%. A single input interface buffer can be designed to meet the V
is intended to specify the center point of the V
Preliminary Information
0 < V
0 < V
4x Mode
Electrical Data
Condition
Condition
IN
IN
< V
< V
REF
REF
DDQ
DDQ
can be designed with 2% resistors to achieve the specified minimum
and I
REF
specifications and to facilitate a common reference circuit.
0.39 V
0.48 V
DDQ
Min
Min
–1
–1
–1
references the I/O ring supply voltage and not the
DDQ
DDQ
REF
is not supplied via the connector.)
IL
/V
IH
0.41 V
0.52 V
range. For the 3.3-V signalling case, at
Max
Max
8
2
8
2
1
10
5
DDQ
DDQ
24416C—December 2001
IL
/V
Units
Units
IH
pF
pF
pF
pF
V
V
A
A
levels of both the
Chapter 4
REF
Notes
Notes
3, 4
3, 4
1, 2
1, 2
2
3
2
3
is 0.4