AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 56

• Manufacturer Part Number: AMD-762JLC
• Description: System Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD-762™ System Controller Data Sheet
Table 5: AMD-762™ System Controller PCI NAND Tree Ordering
3.3
44
Order
20
10
11
12
13
14
15
16
17
18
19
21
1
2
3
4
5
6
7
8
9
AD[31]
REQ[6]#
GNT[5]#
REQ[5]#
GNT[6]#
REQ[4]#
AD[29]
AD[27]
REQ[3]#
AD[25]
GNT[4]#
CBE[3]#
AD[17]
REQ[2]#
REQ[1]#
AD[21]
REQ[0]#
CBE[2]#
AD[23]
AD[30]
IRDY#
Input Pin Name
PLL Bypass Test Mode
AA-27
AH-17
AJ-18
AH-18
AG-17
AJ-19
AE-16
AF-17
AH-19
AE-17
AG-18
AF-18
AE-19
AH-20
AH-21
AF-19
AG-21
AF-20
AE-18
AH-22
AE-20
PLL bypass test mode provides a method to clock the
Northbridge core logic directly from an external source without
the need for the internal PLLs of the AMD-762 system
controller. This test mode is sometimes useful for motherboard
debug and is required in the three-state and NAND tree test
modes.
PLL bypass mode is entered by asserting the TEST# pin Low
and pulling the AD[09] pin High. There are two clocking
Ball
Order
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Preliminary Information
CBE[1]#
DEVSEL#
AD[28]
AD[26]
SERR#
AD[24]
AD[19]
AD[12]
AD[18]
AD[14]
AD[22]
AD[20]
AD[16]
TRDY#
AD[08]
STOP#
AD[10]
FRAME#
PAR
AD[07]
AD[15]
Input Pin Name
Test
AF-22
AF-21
AJ-23
AH-23
AE-21
AG-23
AJ-24
AF-23
AJ-25
AE-22
AH-24
AG-24
AH-25
AJ-26
AF-24
AH-26
AE-23
AG-25
AJ-27
AE-24
AH-27
Ball
Order
43
44
45
46
47
48
49
50
52
53
54
55
56
51
AD[05]
AD[13]
AD[03]
AD[01]
AD[11]
AD[00]
SBGNT#
AD[09]
WSC#
AD[06]
CBE[0]#
SBREQ#
AD[04]
AD[02]
Input Pin Name
24416C—December 2001
Chapter 3
AF-25
AG-27
AE-25
AF-26
AH-28
AE-26
AD-25
AG-28
AC-25
AF-27
AG-29
AE-27
AF-28
AF-29
Ball