AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 42

• Manufacturer Part Number: AMD-762JLC
• Description: System Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD-762™ System Controller Data Sheet
Figure 10.
2.6.5
30
RASn#/CASn#/WEn#
Note: Circled numbers correspond to “S1 Sequence” on page 28.
CLKOUTH[n]
CLKOUTL[n]
DCSTOP#
MAA[14:0]
MAB[14:0]
STPCLK#
CPU BUS
PCI BUS
DQS[8:0]
Power On Suspend System Timing Diagram Example
CKEA
CKEB
Suspend to RAM (S3)
Drive n by the A M D -762™
System Controller during
DRAM Write Cycles.
Running Full Speed
Running Full Speed
This state is exited when the DCSTOP# signal is deasserted by
the Southbridge, followed by a deassertion of STPCLK#. This
action causes the AMD-762 system controller to enable the
clock trees and prepare to reconnect the processor. The
processors assert their respective PROCRDY signal, which
causes the AMD-762 system controller to exit self-refresh and
reconnect the AMD Athlon processor system buses. The
A M D -7 6 2 s y s t e m c o n t ro l l e r re t a i n s t h e s t a t e o f a l l
configuration registers during the S1 state.
The S3 state is similar to S1. However, power is removed from
most of t he motherboard except the A MD-762 system
controller, DRAM, and a portion of the Southbridge. S3 is the
2
3
Preliminary Information
Functional Operation
4
5
6
Enter Self-Refresh
Stop Grant Special Cycle
7
Stop Grant Special Cycle
8
S1 Sleep State
240 s
24416C—December 2001
Chapter 2