AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 24

• Manufacturer Part Number: AMD-762JLC
• Description: System Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD-762™ System Controller Data Sheet
Figure 5.
2.2.1
12
AMD-762™ System Controller
AMD-762™ System Controller Connection to DDR DIMMs
System Clock
DRAM Refresh
The AMD-762 system controller keeps track of when each of
C S[ 7 : 0 ] n e e ds t o b e re f re s he d. E a ch C S i s re f re s h e d
independently. Refresh is only performed on rows that are
populated. A concurrent refresh cycle can be executed in
parallel with other read and write requests, if there is no CS
conflict and the command bus is free. Figure 6 on page 13
shows DRAM refresh timing.
Refresh rates are programmable by BIOS and can accommodate
various rates at 100-MHz or 133-MHz system bus speeds.
CS[3:0]#
MAA[14:00], MAB[14:00]
MDAT[63:00], MECC[7:0]
DQS[8:0]
DM[8:0]
CS[7:4]#
CLKOUTL[3],CLKOUTH[3]
CLKOUTL[0],CLKOUTH[0]
(MAA to even DIMMs,
MAB to odd DIMMs)
RASA#, CASA#, WEA#
RASB#, CASB#, WEB#
CKEA
CKEB
CLKOUTL[2],CLKOUTH[2]
CLKOUTL[1],CLKOUTH[1]
(One pair of CS per DIMM)
Preliminary Information
Functional Operation
DIMMs 0,1
Differential
Clock Pairs
(1 per DIMM)
24416C—December 2001
DIMMs 2,3
Chapter 2