AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 15
AMD-762JLC
Manufacturer Part Number
AMD-762JLC
Description
System Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AMD-762JLC.pdf
(122 pages)
- Current page: 15 of 122
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24416C—December 2001
1.3
Chapter 1
PCI Bus Controller
n BIOS-configurable
n 2.5-V memory interface operation with no external buffers
n Concurrent DRAM writeback and read-around-write
n Burst read and write transactions
n Decoupled and burst DRAM refresh with staggered CS
n Provides the following refresh options:
The PCI bus controller has the following features:
n Compliance with PCI Local Bus Specification, Revision 2.2.
n Supports up to seven PCI bus masters plus the AMD-766
n 64-bit interface, compatible with 3.3-V and 5-V PCI I/O
n Synchronous PCI bus operation up to 66 MHz
n PCI-initiator peer concurrency
n Automatic processor-to-PCI burst cycle detection
n Zero wait-state PCI initiator and target burst transfers
n Enhanced PCI command optimization, such as Memory
configuration parameters
or PLLs
timing
•
•
•
•
peripheral bus controller when operating in 33-MHz-only mode,
or up to two PCI bus masters and the AMD-768 peripheral bus
controller when operating in 66/33-MHz PCI mode.
Read Line (MRL), Memory Read Multiple (MRM), and
Memory-Write-and-Invalidate (MWI)
Programmable refresh rate
CAS-before-RAS
Populated banks only
Automatic refresh of idle slots—improves bus availability
for memory access by the processor or system
Features
memory-timing
AMD-762™ System Controller Data Sheet
parameters
and
3
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