S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 176

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

2.3.104 Port F Reduced Drive Register (RDRF)

2.3.105 Port F Pull Device Enable Register (PERF)

Address 0x037B

Address 0x037C

Write: Anytime.

Port F reduced drive—Select reduced drive for outputs

This register conﬁgures the drive strength of output pins 7 through 0 as either full or reduced independent of the

function used on the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Port F pull device enable—Enable pull devices on input pins

These bits conﬁgure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect

if the pin is used as an output. Out of reset all pull devices are enabled.

1 Pull device enabled.

0 Pull device disabled.

Due to internal synchronization circuits, it can take up to 2 bus clock cycles

until the correct value is read on PTF or PTIF registers, when changing the

DDRF register.

Figure 2-103. Port F Pull Device Enable Register (PERF)

Figure 2-102. Port F Reduced Drive Register (RDRF)

Table 2-100. PERF Register Field Descriptions

Table 2-99. RDRF Register Field Descriptions

MC9S12XE-Family Reference Manual Rev. 1.24

Access: User read/write

Freescale Semiconductor