S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 716

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
To calculate the output frequency in left aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
As an example of a left aligned output, consider the following case:
The output waveform generated is shown in
19.4.2.6
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the
corresponding PWM output will be center aligned.
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Duty Cycle = [PWMDTYx / PWMPERx] * 100%
PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Clock Source = E, where E = 10 MHz (100 ns period)
PWMx Frequency = 10 MHz/4 = 2.5 MHz
PWMx Period = 400 ns
PWMx Duty Cycle = 3/4 *100% = 75%
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
Center Aligned Outputs
PPOLx = 0
PPOLx = 1
E = 100 ns
Figure 19-21. PWM Left Aligned Output Example Waveform
Figure 19-20. PWM Left Aligned Output Waveform
MC9S12XE-Family Reference Manual Rev. 1.24
PWMDTYx
Period = 400 ns
Figure
Duty Cycle = 75%
Period = PWMPERx
19-21.
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