S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 393

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S912XEQ384J3MALR

Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
AND
Operation
RS1 & RS2
RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8])
Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
AND RD, RS1, RS2
AND RD, #IMM16
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to ANDH instruction for #IMM16 operations.
0; cleared.
Not affected.
Z
V
0
Source Form
⇒ RD
When using immediate addressing mode (AND RD, #IMM16), the Z-flag
of the first instruction (ANDL RD, #IMM16[7:0]) is not considered by the
second instruction (ANDH RD, #IMM16[15:8]).
⇒ Don’t rely on the Z-Flag.
C
MC9S12XE-Family Reference Manual Rev. 1.24
Address
Mode
IMM8
IMM8
TRI
Logical AND
0
1
1
NOTE
0
0
0
0
0
0
1
0
0
0
0
1
Machine Code
RD
RD
RD
RS1
IMM16[15:8]
IMM16[7:0]
Chapter 10 XGATE (S12XGATEV3)
RS2
AND
0
0
Cycles
P
P
P
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