S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 781

• Manufacturer Part Number: S912XEQ384J3MALR
• Description: S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
• Manufacturer: Freescale Semiconductor

The SS line can remain active low between successive transfers (can be tied low at all times). This format
is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data
line.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one
half SCK cycle after the last SCK edge.
21.4.4
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2,
SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in
the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits
(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor
equation is shown in
Freescale Semiconductor
•
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
t
t
t
Figure 21-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1)
MOSI pin
MISO pin
L
T
I
Back-to-back transfers in master mode
In master mode, if a transmission has completed and new data is available in the SPI data register,
this data is sent out immediately without a trailing and minimum idle time.
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
= Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
= Minimum leading time before the first SCK edge, not required for back-to-back transfers
= Minimum trailing time after the last SCK edge
SPI Baud Rate Generation
Equation
t
L
1
MSB
LSB
2
BaudRateDivisor = (SPPR + 1) • 2
3
Bit 14
Bit 1
4
21-3.
MC9S12XE-Family Reference Manual Rev. 1.24
5
Bit 13
Begin
Bit 2
6
7
Bit 12
Bit 3
8
9
Bit 11
Bit 4
10
11
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 5
12
13
Bit 6
14
Transfer
15
Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14
16
17
18
19
20
(SPR + 1)
21
Bit 5
22
23
Chapter 21 Serial Peripheral Interface (S12SPIV5)
Bit 4 Bit 3 Bit 2 Bit 1
24
25
End
26
27
28
29
30
31
MSB
LSB
32
t
T
Begin of Idle State
t
I
Minimum 1/2 SCK
for t
t
L
T
, t
l
, t
L
Eqn. 21-3
781