S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 452
S912XEQ384J3MALR
Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ384J3MAL.pdf
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Chapter 10 XGATE (S12XGATEV3)
STW
Operation
RS ⇒ M[RB, #OFFS5]
RS ⇒ M[RB, RI]
RS ⇒ M[RB, RI];
RI–2 ⇒ RI;
Stores the content of register RS to memory.
CCR Effects
Code and CPU Cycles
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
452
N:
Z:
V:
C:
STW RS, (RB, #OFFS5)
STW RS, (RB, RI)
STW RS, (RB, RI+)
STW RS, (RB, -RI)
—
N
register is written to the memory: RS ⇒ M[RB, RS–2]; RS–2 ⇒ RS
Not affected.
Not affected.
Not affected.
Not affected.
—
Z
—
V
Source Form
—
C
RI+2 ⇒ RI;
RS ⇒ M[RB, RI]
MC9S12XE-Family Reference Manual Rev. 1.24
Address
Mode
IDO5
IDR+
-IDR
IDR
Store Word to Memory
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
Machine Code
RS
RS
RS
RS
RB
RB
RB
RB
RI
RI
RI
Freescale Semiconductor
OFFS5
STW
0
0
1
0
1
0
Cycles
PW
PW
PW
PW
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