S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 314

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S912XEQ384J3MALR

Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
314
Address: 0x0023
CDCM[1:0]
ABCM[1:0]
Reset
Field
3–2
1–0
W
R
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
0
0
7
TRCMOD
TRANGE
TALIGN
= Unimplemented or Reserved
00
01
10
11
00
01
10
11
00
01
10
11
Table
Table
0
0
6
8-16.
8-17.
Table 8-13. TRCMOD Trace Mode Bit Encoding
Table 8-14. TALIGN Trace Alignment Encoding
Figure 8-6. Debug Control Register2 (DBGC2)
Table 8-12. TRANGE Trace Range Encoding
MC9S12XE-Family Reference Manual Rev. 1.24
Table 8-15. DBGC2 Field Descriptions
Trace only in address range from Comparator C to $7FFFFF
Trace only in address range from $00000 to Comparator D
Trace only in range from Comparator C to Comparator D
0
0
5
Trace buffer entries before and after trigger
Trace from all addresses (No filter)
Trigger at end of stored data
Trigger before storing data
0
0
4
Description
Tracing Range
Description
Description
Reserved
Pure PC
Normal
Loop1
Detail
0
3
CDCM
0
2
Freescale Semiconductor
0
1
ABCM
0
0

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