S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 739

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S912XEQ384J3MALR

Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
20.4
This section provides a complete functional description of the SCI block, detailing the operation of the
design from the end user perspective in a number of subsections.
Figure 20-14
communication between the CPU and remote devices, including other CPUs. The SCI transmitter and
receiver operate independently, although they use the same baud rate generator. The CPU monitors the
status of the SCI, writes the data to be transmitted, and processes received data.
Freescale Semiconductor
SBR12:SBR0
Clock
RXD
Bus
Decoder
Functional Description
Infrared
Receive
Baud Rate
Generator
IREN
shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial
Ir_RXD
T8
R16XCLK
R32XCLK
÷16
SCRXD
TNP[1:0]
Shift Register
and Wakeup
Data Format
Transmit
Encoder
Infrared
SCI Data
Transmit
Transmit
Register
Receive
MC9S12XE-Family Reference Manual Rev. 1.24
Control
Control
Control
Figure 20-14. Detailed SCI Block Diagram
SCTXD
IREN
Shift Register
SCI Data
Ir_TXD
Receive
Register
LOOPS
LOOPS
RSRC
WAKE
RSRC
RWU
SBK
RE
ILT
PE
PT
TE
M
RXD
Chapter 20 Serial Communication Interface (S12SCIV5)
TDRE
RDRF
TCIE
TIE
IDLE
RAF
RIE
Break Detect
TC
LIN Transmit
BERRM[1:0]
OR
NF
Active Edge
R8
FE
PF
BKDFE
Collision
Detect
Detect
RXEDGIE
ILIE
BKDIE
BERRIF
RXEDGIF
BKDIF
BERRIE
TDRE
TC
TXD
IDLE
SCI
Interrupt
Request
739

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