S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 484
S912XEQ384J3MALR
Manufacturer Part Number
S912XEQ384J3MALR
Description
S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ384J3MAL.pdf
(1324 pages)
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.3.2.10 Reserved Register (FORBYP)
Read: Always read $00 except in special modes
Write: Only in special modes
11.3.2.11 Reserved Register (CTCTL)
Read: Always read $00 except in special modes
484
Module Base + 0x0009
Module Base + 0x000A
Reset
Reset
W
W
R
R
0
0
0
0
7
7
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the S12XECRG’s functionality.
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the S12XECRG’s functionality.
= Unimplemented or Reserved
= Unimplemented or Reserved
1. OSCCLK cycles are referenced from the previous COP time-out reset
(writing $55/$AA to the ARMCOP register)
CR2
0
0
0
0
6
6
1
Figure 11-12. Reserved Register (FORBYP)
MC9S12XE-Family Reference Manual Rev. 1.24
Figure 11-13. Reserved Register (CTCTL)
Table 11-13. COP Watchdog Rates
CR1
1
0
0
0
0
5
5
CR0
1
NOTE
NOTE
0
0
0
0
4
4
Cycles to Timeout
0
0
0
0
3
3
OSCCLK
2
24
(1)
0
0
0
0
2
2
Freescale Semiconductor
0
0
0
0
1
1
0
0
0
0
0
0
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