LPC1778FBD144,551 NXP Semiconductors, LPC1778FBD144,551 Datasheet - Page 115

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LPC1778FBD144,551

Manufacturer Part Number
LPC1778FBD144,551
Description
ARM Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM USB 2.0
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1778FBD144,551

Rohs
yes
Core
ARM Cortex M3
Processor Series
LPC178x
Data Bus Width
32 bit
Maximum Clock Frequency
120 MHz
Program Memory Size
512 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 3.6 V
Package / Case
LQFP-144
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Interface Type
CAN, I2C, I2S, SSP
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
165
Number Of Timers
4
On-chip Dac
Yes
Program Memory Type
Flash
Factory Pack Quantity
60
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.4 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1778FBD144,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
18. Revision history
Table 35.
LPC178X_7X
Product data sheet
Document ID
LPC178X_7X v.4.1
Modifications:
LPC178X_7X v.4
Modifications:
LPC178X_7X v.3
Revision history
20121115
Release date
20120501
20111220
LCD timing characteristics updated in
Figure 26
Removed table note “The peak current is limited to 25 times the corresponding maximum
current.” in
Removed deep power-down spec
Updated min value for t
Removed Fig 21 Internal RC oscillator frequency versus temperature.
Updated 12-bit and 8-bit values for E
Changed data sheet status to Product.
Editorial updates.
BOD values added in Section 7.34.2.
Parameters t
C
I
Deep-power down mode.
I
Power consumption data in Figure 9 and Figure 10 corrected.
I/O voltage V
V
Parameter C
USB and Ethernet dynamic characteristics removed. Timing characteristics follow USB 2.0
Specification (full speed) and IEEE standard 802.3. standards (see Section 7.15 and
Section 7.14 for compliance statements).
Pad characteristics updated in Table 3.
Parameter I
Figure 11 added.
SDRAM timing corrected in Figure 19.
EEPROM erase and programming times added (Table 16).
Data sheet status changed to preliminary.
DD(REG)(3V3)
BAT
DD(3V3)
L
= 10 pF added to Table 24, Table 26, Table 28.
corrected in Table 13 for condition Deep power-down mode.
range corrected in Table 23.
All information provided in this document is subject to legal disclaimers.
added.
Table
BAT
corrected in Table 13 for conditions Deep-sleep mode, Power-down mode, and
CSLBLSL
L
DD(3V3)
Data sheet status
Product data sheet
Preliminary data sheet
changed to 10 pF for EMC timing in Table 17 to Table 20.
Objective data sheet
Rev. 4.1 — 15 November 2012
updated in Table 13.
9.
specified in Table 17, Table 18, Table 19, Table 24, Table 28.
, t
CSHOEH
WEHEOW
, t
OEHANV
Table
Table 13
T
Table 27 “Dynamic characteristics: LCD”
15.
Table
, t
deact
and associated table note.
Change notice
-
29.
-
-
, t
32-bit ARM Cortex-M3 microcontroller
BLSHEOW
, t
BLSHDNV
LPC178x/7x
Supersedes
LPC178X_7X v.4
LPC178X_7X v.3
LPC178X_7X v.2
updated in Table 17.
© NXP B.V. 2012. All rights reserved.
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