LPC1778FBD144,551 NXP Semiconductors, LPC1778FBD144,551 Datasheet - Page 83

• Manufacturer Part Number: LPC1778FBD144,551
• Description: ARM Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM USB 2.0
• Manufacturer: NXP Semiconductors

Specifications of LPC1778FBD144,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC178x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Interface Type: CAN, I2C, I2S, SSP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• On-chip Dac: Yes
• Program Memory Type: Flash
• Factory Pack Quantity: 60
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V

NXP Semiconductors
Table 17.
C
[1]
[2]
[3]
[4]
[5]
[6]
LPC178X_7X
Product data sheet
Symbol
t
t
t
BLSLBLSH
BLSHEOW
BLSHDNV
Fig 16. External static memory read/write access (PB = 0)
L
= 10 pF, T
Parameters are shown as RD
Parameters specified for 40 % of V
T
Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
cy(clk)
EMC_BLSx
EMC_CSx
EMC_WE
EMC_OE
EMC_Ax
EMC_Dx
= 1/CCLK (see LPC178x/7x User manual UM10470).
Dynamic characteristics: Static external memory interface
Parameter
BLS LOW to BLS HIGH time WR
BLS HIGH to end of write
time
BLS HIGH to data invalid
time
amb
=

40

[1]
C to 85
n

or WD
C, V
DD(3V3)
RD
DD(3V3)
n
RD
2
in
1
Figure 16
RD
for rising edges and 60 % of V
Conditions
WR
WR12;
PB = 0
All information provided in this document is subject to legal disclaimers.
5
= 3.0 V to 3.6 V. Values guaranteed by design.
10
11
; PB = 0
Rev. 4.1 — 15 November 2012
; PB = 0
RD
RD
as indicated in the Conditions column.
5
RD
5
4
[1]
[3]
[6]
[3]
[3]
Min
(WAITWR  WAITWEN +
3)  T
1.3 + T
1.4 + T
EOR
RD
RD
cy(clk)
6
cy(clk)
cy(clk)
DD(3V3)
7
 1.4
WR
…continued
for falling edges.
WR
2
9
32-bit ARM Cortex-M3 microcontroller
WR
WR
1
10
Max
(WAITWR  WAITWEN +
3)  T
2.2 + T
2.7 + T
WR
12
WR
cy(clk)
cy(clk)
cy(clk)
LPC178x/7x
11
 2.7
EOW
© NXP B.V. 2012. All rights reserved.
WR
002aag214
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Unit
ns
ns
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