LPC1778FBD144,551 NXP Semiconductors, LPC1778FBD144,551 Datasheet - Page 82

• Manufacturer Part Number: LPC1778FBD144,551
• Description: ARM Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM USB 2.0
• Manufacturer: NXP Semiconductors

Specifications of LPC1778FBD144,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC178x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Interface Type: CAN, I2C, I2S, SSP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• On-chip Dac: Yes
• Program Memory Type: Flash
• Factory Pack Quantity: 60
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V

NXP Semiconductors
Table 17.
C
LPC178X_7X
Product data sheet
Symbol
Read cycle parameters
t
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
t
t
t
t
t
CSLAV
CSLOEL
CSLBLSL
OELOEH
am
h(D)
CSHBLSH
CSHOEH
OEHANV
deact
CSLAV
CSLDV
CSLWEL
CSLBLSL
WELWEH
BLSLBLSH
WEHDNV
WEHEOW
BLSHDNV
WEHANV
deact
CSLBLSL
L
= 10 pF, T
Dynamic characteristics: Static external memory interface
Parameter
CS LOW to address valid
time
CS LOW to OE LOW time
CS LOW to BLS LOW time
OE LOW to OE HIGH time
memory access time
data input hold time
CS HIGH to BLS HIGH time PB = 1
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
deactivation time
CS LOW to address valid
time
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH time PB = 1
WE HIGH to data invalid
time
WE HIGH to end of write
time
BLS HIGH to data invalid
time
WE HIGH to address invalid
time
deactivation time
CS LOW to BLS LOW
amb
11.2 External memory interface
=

40

[1]
C to 85
[2]
[2]

C, V
DD(3V3)
Conditions
RD
RD
RD
RD
RD
RD
RD
WR
WR
WR
WR
WR
WR
WR
PB = 1
PB = 1
WR
PB = 1
WR
All information provided in this document is subject to legal disclaimers.
= 3.0 V to 3.6 V. Values guaranteed by design.
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
; PB = 1
; PB =1
; PB = 1
; PB =1
; PB =1
; PB = 1
; PB = 0;
; PB = 0
Rev. 4.1 — 15 November 2012
[1]
[3]
[3]
[3]
[4]
[3]
[5]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[6]
[3]
[3]
[3]
[3]
Min
1.4
1.3 + T
1.5
(WAITRD  WAITOEN +
1)  T
(WAITRD 
WAITOEN +1) T
7.2
0.1
1.5
1.3
0.09
1.4
1.4
1.5
1.4 + T
(1 + WAITWEN)
3.0
(WAITWR  WAITWEN +
1)  T
(WAITWR  WAITWEN +
3)  T
1.2 + T
T
1.4
1 + T
1.4
3.0 + T
(1 + WAITWEN)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
 1.4
cy(clk)
cy(clk)
cy(clk)
cy(clk)
 1.0
 1.0
 1.4

 WAITOEN 2.5 + T

32-bit ARM Cortex-M3 microcontroller
cy(clk)

Max
2.5
3.0
(WAITRD  WAITOEN +
1)  T
(WAITRD 
WAITOEN +1) 
T
0.1
3.0
2.5
0.13
2.5
2.5
2.9
2.5 + T
(1 + WAITWEN)
3.0
(WAITWR  WAITWEN +
1)  T
(WAITWR  WAITWEN +
3)  T
2.1 + T
T
2.7
1.7 + T
2.5
3.0 + T
(1 + WAITWEN)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
 15.5
 2.5
cy(clk)
cy(clk)
cy(clk)
cy(clk)
cy(clk)
LPC178x/7x
 1.6
 1.7
 2.7

 WAITOEN ns

© NXP B.V. 2012. All rights reserved.
82 of 120
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns