Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 129
Z8F041APH020SG2156
Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet
1.Z8F082ASJ020EG2156.pdf
(282 pages)
Specifications of Z8F041APH020SG2156
Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
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PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7,5]
MPMD[1,0]
[6]
MPEN
[4]
MPBT
[3]
DEPOL
MPMD[1]
Description
MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) Mode is enabled:
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
11 = The UART generates an interrupt request on all received data bytes for which the most
MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) Mode.
0 = Disable MULTIPROCESSOR (9-bit) Mode.
1 = Enable MULTIPROCESSOR (9-bit) Mode.
Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) Mode is enabled. The 9th bit is
used by the receiving device to determine if the data byte contains address or data informa-
tion.
0 = Send a 0 in the multiprocessor bit location of the data stream (data byte).
1 = Send a 1 in the multiprocessor bit location of the data stream (address byte).
Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
R/W
7
0
value stored in the Address Compare Register and on all successive data bytes until
an address mismatch occurs.
recent address byte matched the value in the Address Compare Register.
MPEN
R/W
6
0
Table 64. UART Control 1 Register (U0CTL1)
MPMD[0]
R/W
5
0
P R E L I M I N A R Y
MPBT
R/W
4
0
F43H
DEPOL
R/W
3
0
Z8 Encore! XP
UART Control Register Definitions
BRGCTL
R/W
2
0
Product Specification
RDAIRQ
R/W
1
0
®
F082A Series
IREN
R/W
0
0
112
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