C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 112
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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C8051F52x/F53x
SFR Definition 11.2. RSTSRC: Reset Source
112
Note: Software should avoid read modify write instructions when writing values to RSTSRC.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
—
UNUSED. Read = 1, Write = don't care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0.
1: Read: Source of last reset was Comparator0.
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit.
1: Read: Source of last reset was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout.
1: Read: Source of last reset was a Missing Clock Detector timeout.
detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
monitor (VDDMON0) as a reset source. Note: writing 1 to this bit before the V
tor is enabled and stabilized may cause a system reset. See register VDDMON (SFR
Definition 11.1)
0: Read: Last reset was not a power-on or V
1: Read: Last reset was a power-on or V
nate.
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
FERROR C0RSEF
Write: Comparator0 is not a reset source.
Write: Comparator0 is a reset source (active-low).
Write: No Effect.
Write: Forces a system reset.
Write: Missing Clock Detector disabled.
Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
Write: V
Write: V
Bit6
R
DD
DD
monitor (VDDMON0) is not a reset source.
monitor (VDDMON0) is a reset source.
R/W
Bit5
SWRSF
R/W
Bit4
WDTRSF MCDRSF
Rev. 1.4
Bit3
R
DD
monitor reset; all other reset flags indetermi-
DD
monitor reset.
R/W
Bit2
PORSF
R/W
Bit1
SFR Address:
PINRSF
Bit0
R
DD
Reset Value
Variable
moni-
0xEF
DD
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