C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 207
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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SFR Definition 19.2. PCA0MD: PCA Mode
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
Bit0:
Note: When the WDTE bit is set to 1, the PCA0MD register cannot be modified. To change the
CIDL
R/W
Bit7
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
UNUSED. Read = 0b, Write = don't care.
These bits select the timebase source for the PCA counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Note: External clock divided by 8 is synchronized with the system clock.
CPS2
WDTE
0
0
0
0
1
1
1
1
R/W
Bit6
CPS1
WDLCK
0
0
1
1
0
0
1
1
R/W
Bit5
CPS0
0
1
0
1
0
1
0
1
Bit4
R
-
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8
Reserved
Reserved
Rev. 1.4
CPS2
R/W
Bit3
CPS1
R/W
Bit2
Timebase
*
C8051F52x/F53x
.
CPS0
R/W
Bit1
SFR Address: 0xD9
ECF
R/W
Bit0
01000000
Reset Value
207
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