C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 6
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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C8051F52x/F53x
19. Programmable Counter Array (PCA0)................................................................ 195
20. Device Specific Behavior .................................................................................... 210
21. C2 Interface .......................................................................................................... 214
Document Change List.............................................................................................. 217
Contact Information................................................................................................... 220
6
19.1. PCA Counter/Timer ....................................................................................... 196
19.2. Capture/Compare Modules ........................................................................... 197
19.3. Watchdog Timer Mode .................................................................................. 203
19.4. Register Descriptions for PCA....................................................................... 206
20.1. Device Identification ...................................................................................... 210
20.2. Reset Pin Behavior........................................................................................ 211
20.3. Reset Time Delay .......................................................................................... 211
20.4. VDD Monitors and VDD Ramp Time ............................................................. 211
20.5. VDD Monitor (VDDMON0) High Threshold Setting ....................................... 212
20.6. Reset Low Time............................................................................................. 212
20.7. Internal Oscillator Suspend Mode ................................................................. 212
20.8. UART Pins..................................................................................................... 213
20.9. LIN ................................................................................................................. 213
21.1. C2 Interface Registers................................................................................... 214
21.2. C2 Pin Sharing .............................................................................................. 216
19.2.1. Edge-triggered Capture Mode............................................................... 198
19.2.2. Software Timer (Compare) Mode.......................................................... 199
19.2.3. High Speed Output Mode...................................................................... 200
19.2.4. Frequency Output Mode ....................................................................... 201
19.2.5. 8-Bit Pulse Width Modulator Mode........................................................ 202
19.2.6. 16-Bit Pulse Width Modulator Mode...................................................... 203
19.3.1. Watchdog Timer Operation ................................................................... 204
19.3.2. Watchdog Timer Usage ........................................................................ 205
20.9.1. Stop Bit Check ...................................................................................... 213
20.9.2. Synch Break and Synch Field Length Check........................................ 213
Rev. 1.4
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