C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 218
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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C8051F52x/F53x
Revision 1.2 to 1.3
Revision 1.3 to 1.4
218
Updated “System Overview” on page 13 with a voltage range specification for the internal oscillator.
Updated Table 2.11 on page 34 with new conditions for the internal oscillator accuracy. The internal
oscillator accuracy is dependent on the operating voltage range.
Updated Section 2 to remove the internal oscillator curve across temperature diagram.
Updated Figure “4.5 12-Bit ADC Burst Mode Example with Repeat Count Set to 4” on page 58 with new
timing diagram when using CNVSTR pin.
Updated SFR Definition 5.1 (REF0CN) with oscillator suspend requirement for ZTCEN.
Updated SFR Definition 6.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and
must be written to 1b.
Updated Section “8.3.3. Suspend Mode” on page 90 with note regarding ZTCEN.
Updated Section “17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A)” on page 164 with
a voltage range specification for the internal oscillator.
Added ‘AEC-Q100’ qualification information on page 1.
Changed page headers throughout the document from ‘C8051F52x/F52xA/F53x/F53xA’ to
‘C8051F52x/53x’.
Updated supply voltage to "2.0 to 5.25 V" on page 1 and in Section 1 on page 13.
Corrected reference to development kit (C8051F530DK) in Section “1.2.4. On-Chip Debug Circuitry” on
page 18.
Updated minimum Supply Input Voltage (V
page 26 and Table 2.6 on page 30.
Updated digital supply current (I
Table 2.2 on page 26.
Updated I
removed Figure 2.1 and Figure 2.2 that used to provide the same frequency sensitivity slopes. Also
removed IDD Supply Sensitivity and Idle IDD Supply Sensitivity typical values.
Added Digital Supply Current (Stop or Suspend Mode) values at multiple temperatures Table 2.2 on
page 26.
Added a note in Table 2.3, “ADC0 Electrical Characteristics,” on page 28 with reference to
“4.4. Selectable Gain” on page 60
necessary if VDD is less than the minimum specified VDD.
Split off temperature sensor specifications from Table 2.3 into a separate table Table 2.4; Updated
temperature sensor gain and added supply current values.
Added temperature condition for Bias Current specification in Table 2.6 on page 30.
Updated Comparator Input Offset Voltage values in Table 2.7 on page 31.
Updated VDD Monitor (VDDMON0) Low Threshold (V
C/F53xA/F53x-C devices in Table 2.8 on page 32.
Updated VDD Monitor (VDDMON0) supply current values in Table 2.8 on page 32.
Added specifications for the new level-sensitive VDD monitor (VDDMON1) to Table 2.8, “Reset
Electrical Characteristics,” on page 32 and also added notes to clarify the applicable V
level.
Added note in Table 2.9, “Flash Electrical Characteristics,” on page 33 to describe the minimum flash
programming temperature for –I (Industrial Grade) devices; Also added the same note and references
to it in Section “12.1. Programming The Flash Memory” on page 113, Section “12.3. Non-volatile Data
Storage” on page 117, and in SFR Definition 12.1 (PSCTL).
DD
Frequency Sensitivity and Idle I
; also added note to indicate that additional tracking time may be
DD
and Idle I
REGIN
DD
DD
Rev. 1.4
) typical values for condition ‘Clock = 25 MHz’ in
Frequency Sensitivity values in Table 2.2 on page 26;
) for C8051F52x-C/F53x-C devices in Table 2.2 on
RST-LOW
) minimum value for C8051F52xA/F52x-
RST
Section
theshold
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