C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 170
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C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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10.Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
C8051F52x/F53x
17.4. LIN Slave Mode Operation
When the device is configured for slave mode operation, it must wait for a command from a master node.
Access from the firmware to data buffer and ID registers of the LIN peripheral is only possible when a data
request is pending (DTREQ bit (LIN0ST.4) is 1) and also when the LIN bus is not active (ACTIVE bit
(LIN0ST.7) is set to 0).
The LIN peripheral in slave mode detects the header of the message frame sent by the LIN master. If slave
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.
The LIN peripheral configured for slave mode will generated an interrupt in one of three situations:
1. After the reception of the IDENTIFIER FIELD.
2. When an error is detected.
3. When the message transfer is completed.
The application should perform the following steps when an interrupt is detected:
1. Check the status of the DTREQ bit (LIN0ST.4). This bit is set when the IDENTIFIER FIELD has been
2. If DTREQ (LIN0ST.4) is set, read the identifier from LIN0ID and process it. If DTREQ (LIN0ST.4) is not
3. Set the TXRX bit (LIN0CTRL.5) to 1 if the current frame is a transmit operation for the slave and set to
4. Load the data length into LIN0SIZE.
5. For a slave transmit operation, load the data to transmit into the data buffer.
6. Set the DTACK bit (LIN0CTRL.4). Continue to step 10.
7. If DTREQ (LIN0ST.4) is not set, check the DONE bit (LIN0ST.0). The transmission was successful if the
8. If the transmission was successful and the current frame was a receive operation for the slave, load the
9. If the transmission was not successful, check LIN0ERR to determine the nature of the error. Further
In addition to these steps, the application should be aware of the following:
1. If the current frame is a transmit operation for the slave, steps 1 through 5 must be completed during
2. If the current frame is a receive operation for the slave, steps 1 through 5 have to be finished until the
3. The LIN module does not directly support LIN Version 1.3 Extended Frames. If the application detects
4. Changing the configuration of the checksum during a transaction will cause the interface to reset and
170
received.
set, continue to step 7.
0 if the current frame is a receive operation for the slave.
DONE bit is set.
received data bytes from the data buffer.
error handling has to be done by the application.
error flags.
the IN-FRAME RESPONSE SPACE. If it is not completed in time, a timeout will be detected by the
master.
reception of the first byte after the IDENTIFIER FIELD. Otherwise, the internal receive buffer of the LIN
peripheral will be overwritten and a timeout error will be detected in the LIN peripheral.
an unknown identifier (e.g. extended identifier), it has to write a 1 to the STOP bit (LIN0CTRL.7) instead
of setting the DTACK (LIN0CTRL.4) bit. At that time, steps 2 through 5 can then be skipped. In this
situation, the LIN peripheral stops the processing of the LIN communication until the next SYNC
BREAK is received.
the transaction to be lost. To prevent this, the checksum should not be configured while a transaction is
Rev. 1.4
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