C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 51
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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Table 3.9. QFN-20 Landing Diagram Dimensions
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD).
4. A stainless steel, laser-cut and electro-polished stencil with
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-
Symbol
noted.
Clearance between the solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
trapezoidal walls should be used to assure good solder paste
release.
perimeter pads.
used for the center ground pad.
020 specification for Small Body Components.
C1
C2
X1
X2
Y1
Y2
E
Rev. 1.4
3.90
3.90
0.20
2.75
0.65
2.75
Min
0.50 BSC.
C8051F52x/F53x
Max
4.00
4.00
0.30
2.85
0.75
2.85
51
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