C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 23
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C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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1.6. Programmable Comparator
C8051F52x/F52xA/F53x/F53xA devices include a software-configurable voltage comparator with an input
multiplexer. The comparator offers programmable response time and hysteresis and an output that is
optionally available at the Port pins: a synchronous “latched” output (CP0). The comparator interrupt may
be generated on rising, falling, or both edges. When in IDLE or SUSPEND mode, these interrupts may be
used as a “wake-up” source for the processor. The Comparator may also be configured as a reset source.
A block diagram of the comparator is shown in Figure 1.8.
1.7. Voltage Regulator
C8051F52x/F52xA/F53x/F53xA devices include an on-chip low dropout voltage regulator (REG0). The
input to REG0 at the V
2.6 V. When enabled, the output of REG0 powers the device and drives the V
can be used to power external devices connected to V
1.8. Serial Port
The C8051F52x/F52xA/F53x/F53xA family includes a full-duplex UART with enhanced baud rate configu-
ration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and
makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
Port I/O
Pins
REGIN
pin can be as high as 5.25 V. The output can be selected by software to 2.1 or
Figure 1.8. Comparator Block Diagram
+
-
VDD
GND
Decision
Reset
Rev. 1.4
Tree
DD
(SYNCHRONIZER)
D
SET
CLR
.
Q
Q
D
SET
CLR
Interrupt
Q
Q
Logic
C8051F52x/F53x
DD
pin. The voltage regulator
(asynchronous output)
(synchronous output)
CP0A
CP0
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