C8051F537-ITR Silicon Labs, C8051F537-ITR Datasheet - Page 115
![no-image](/images/no-image-200.jpg)
C8051F537-ITR
Manufacturer Part Number
C8051F537-ITR
Description
8-bit Microcontrollers - MCU 2KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F537-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
2 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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12.2. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
12.2.1. V
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
2. Make certain that the maximum V
3. Enable the on-chip V
4. As an added precaution, explicitly enable the V
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
12.2.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set to a 1. There should be
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
4. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
page 211 for more details on V
then add an external V
until V
V
possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V
in “AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site.
a reset source inside the functions that write and erase Flash memory. The V
instructions should be placed just after the instruction to set PSWE to a 1, but before the Flash write or
erase operation instruction.
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
PSWE and PSEE both to a 1 to erase Flash pages.
and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing
this can be found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories
web site.
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
DD
DD
monitor (VDDMON0) and enabling it as a reset source. Code examples showing this can be found
(min) is specified in Table 2.2 on page 26.
DD
DD
Maintenance and the V
reaches the minimum specified V
DD
, system clock frequency, or temperature. This accidental execution of Flash modi-
DD
DD
monitor (VDDMON0) and enable it as a reset source as early in code as
brownout circuit to the RST pin of the device that holds the device in reset
DD
DD
DD
ramp time. If the system cannot meet this ramp time specification,
monitor
ramp time specification (if applicable) is met. See Section 20.4 on
DD
Rev. 1.4
and re-asserts RST if V
DD
monitor (VDDMON0) and enable the V
C8051F52x/F53x
DD
drops belowthat level.
DD
monitor enable
DD
monitor as
115
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