ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 29

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
Temperature Linearization Scheme
The
preselected combination of thermistor (100 kΩ, 1%), external
resistor (16.5 kΩ, 1%), and the 46 µA current source for best
performance when linearizing measured temperatures in the
industrial range.
The required NTC thermistor should have a resistance of
100 kΩ, 1%, such as the NCP15WF104F03RC (beta = 4250,
1%). It is recommended that 1% tolerance be used for both the
resistor and beta values.
Reading the Linearized Temperature
Reading Register 0x1B (updated every 10 ms) returns the current
temperature according to an internal linearization scheme. See
Table 1 for the specified accuracy of these measurements. The
temperature reading result is represented in 8-bit decimal format
in °C; therefore, the temperature range for this reading is from
0°C to 255°C.
OVERTEMPERATURE PROTECTION (OTP)
If the temperature sensed at the RTD pin exceeds the threshold
programmed in Register 0x2F, the OTP flag is set. The response
to the OTP flag is programmable using Register 0x0B[7:4].
An RTD trim is required to make accurate temperature readings
at the lower end of the RTD ADC range to account for tolerances
in the NTC thermistor and the external resistor. This trim results
in a more accurate measurement for determining the OTP
threshold (see the RTD/OTP Trim section).
OUTA
OUTB
V
IN
ADP1046
OUTC
OUTD
implements a linearization scheme based on a
CS1
1.2V
COMPARATOR
FAST OCP
Figure 38. CS1 OCP Detailed Internal Schematic
ADC
CS1
FLAGIN
12
REG 0x27[4]
FAST OCP
BYPASS
Rev. B | Page 29 of 92
CS1
2.62ms AVERAGING
ASYNCHRONOUS
CS1 ACCURATE
OCP SETTING
REG 0x22[4:0]
REG 0x22[7:5]
FAST OCP
BLANKING
CS1
OVERCURRENT PROTECTION (OCP)
The
separate OCP circuits to provide both primary and secondary
side protection.
CS1 OCP
CS1 has two protection circuits: CS1 fast OCP and CS1 accurate
OCP (see Figure 38).
CS1 Fast OCP
CS1 fast OCP is an analog comparator. When the voltage at the
CS1 pin exceeds the (fixed) 1.2 V threshold, the CS1 fast OCP
flag is set. A programmable blanking time can be set to ignore
the leading edge current spike at the beginning of the current
signal (leading edge blanking).
A debounce time can be programmed to improve the noise immu-
nity of the OCP circuit. When the CS1 fast OCP comparator is
set, the OUTA, OUTB, OUTC, and OUTD PWM outputs are
immediately disabled for the remainder of the switching cycle.
These outputs are reenabled at the start of the next switching
cycle. This function cannot be bypassed.
CS1 Accurate OCP
CS1 accurate OCP is used for more precise control of overcurrent
protection. With CS1 accurate OCP, the reading at the output of
the CS1 ADC (Register 0x13) is compared to a programmable
OCP limit. The CS1 accurate OCP value can be programmed
from 0 to 31 decimal using Register 0x22[4:0]. If the CS1 reading
exceeds the CS1 accurate OCP limit, the CS1 accurate OCP flag
is set. The CS1 ADC is asynchronously sampled, and the readings
are averaged every 2.62 ms to make a fault decision. The flag
response is programmed in Register 0x08.
ADP1046
REG 0x27[7:6]
DEBOUNCE
FAST OCP
CS1
CS1 ACCURATE
OCP FLAG
has several OCP functions. CS1 and CS2± have
CS1 FAST
REG 0x27[1:0]
OCP
FLAG
TIMEOUT
CYCLE
FLAGS
CYCLE-BY-CYCLE
SHUTDOWN
SHUTDOWN
PWM
ADP1046
OUTA
OUTB
OUTC
OUTD
SR1
SR2
OUTAUX