ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 81

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
Table 124. Register 0x7C—PGOOD2 Flag Masking
Bits
7
6
5
4
3
2
1
0
Table 125. Register 0x7D—Light Load Mode Threshold Settings
Bits
[7:6]
[5:4]
[3:2]
[1:0]
Table 126. Register 0x7F—GO Byte
Bits
[7:4]
3
2
1
0
Bit Name
Soft start flag
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
UVP
Local OVP (fast and
accurate)
Load OVP
OrFET
Bit Name
Reserved
Debounce
Light load mode
averaging speed
Light load mode
hysteresis
Bit Name
Reserved
Filter GO
Frequency GO
PWM settings GO
Voltage reference GO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
Description
Reserved.
After the SR outputs are turned on or off, any further transition of the thresholds is ignored for the
amount of time programmed in these bits. This debounce is provided to avoid false transitions
and improve noise immunity. The debounce time is calculated as a number of PWM switching
cycles (t
Bit 5
0
0
1
1
These bits set the averaging speed and resolution used for the light load mode threshold.
Faster speed corresponds to lower resolution and, therefore, to lower accuracy of the threshold.
Bit 3
0
0
1
1
These bits set the amount of hysteresis applied to the light load mode threshold. The size of the
LSB is affected by the speed and resolution selected in Bits[3:2]. If the CS2 ADC range of 120 mV
is used with 8-bit resolution, the LSB size is 120 mV/2
Bit 1
0
0
1
1
Description
If this bit is set to 1, the soft start flag is ignored by PGOOD2. This bit must be set to 0 to enable
proper PGOOD2 debounce timing after the end of the soft start ramp.
If this bit is set to 1, the CS1 fast OCP flag is ignored by PGOOD2.
If this bit is set to 1, the CS1 accurate OCP flag is ignored by PGOOD2.
If this bit is set to 1, the CS2 accurate OCP flag is ignored by PGOOD2.
If this bit is set to 1, the UVP flag is ignored by PGOOD2.
If this bit is set to 1, the local OVP flag is ignored by PGOOD2.
If this bit is set to 1, the load OVP flag is ignored by PGOOD2.
If this bit is set to 1, the OrFET flag is ignored by PGOOD2.
Description
Reserved.
This bit latches all the filter registers: Register 0x60 to Register 0x67 and Register 0x71 to
Register 0x75.
This bit latches Register 0x3F and Register 0x40. This is to prevent the switching frequency
settings from being temporarily incorrect.
This bit latches Register 0x41 to Register 0x5C. This is to prevent the PWM settings from being
temporarily incorrect.
This bit latches Register 0x31. This is to prevent the reference setting from being temporarily
incorrect.
SW
). For example, at 100 kHz, t
Bit 4
0
1
0
1
Bit 2
0
1
0
1
Bit 0
0
1
0
1
Rev. B | Page 81 of 92
Debounce Time
0 t
64 t
128 t
256 t
Speed (Resolution)
37.5 µs (6 bits)
75 µs (7 bits)
150 µs (8 bits)
300 µs (9 bits)
Hysteresis (LSB)
3
8
12
16
SW
SW
SW
SW
SW
= 10 µs, 64 × t
8
SW
= 469 µV.
= 640 µs.
ADP1046