ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 49

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
DETAILED REGISTER DESCRIPTIONS
FAULT REGISTERS
Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared
only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also
note that these register bits are cleared when read via the I
fault register be read again after the faults disappear to ensure that the register is reset.
Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)
Bits
7
6
5
4
3
2
1
0
Bit Name
Power supply
OrFET
PGOOD1 fault
PGOOD2 fault
SR off
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
Bit Name
Voltage
continuity
UVP
CS2 reverse
current
VDD UV
VCORE OV
VDD OV
Load OVP
Local OVP
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R
R
Description
1 = power supply is off. All PWM outputs are disabled. This bit
stays high until the power supply is restarted.
1 = OrFET control signal at the GATE pin (Pin 16) is off.
1 = Power-Good 1 fault. At least one of the following flags has been
set: soft start flag, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP,
UVP, local OVP, load OVP, or OrFET (GATE pin). These flags can be
masked using Register 0x7B.
1 = Power-Good 2 fault. At least one of the following flags has been
set: soft start flag, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP,
UVP, local OVP, load OVP, or OrFET (GATE pin). These flags can be
masked using Register 0x7C.
The following flags can also set PGOOD2, either unconditionally
or based on the flag response, as defined in Register 0x2D[3] (see
Table 45): voltage continuity, OrFET disable, ACSNS, external flag
(FLAGIN pin), and OTP.
SR1 and SR2 synchronous rectifiers are disabled. This flag is set
when one of the following cases is true:
SR1 and SR2 are disabled by the user.
The load current has fallen below the threshold in Register 0x3B.
A flag has been set that is configured to disable the synchronous
rectifiers.
CS1 current is above its fast overcurrent protection limit. There is a
1.2 V threshold on the CS1 pin. Fast OCP is a comparator.
CS1 current is above its accurate overcurrent protection limit.
CS2 current is above its accurate overcurrent protection limit.
Description
Voltage differential between VS1 and VS2 pins or between VS2
and VS3± pins is outside limits. Either (VS1 − VS2) > 50 mV or
(VS2 − VS3) > 50 mV at the pins.
VS1 is below its undervoltage limit.
Reverse voltage across the CS2± pins is above limit. This is the
OrFET reverse voltage.
VDD is below limit.
2.5 V VCORE is above limit.
VDD is above limit. The I
toggle is required to restart the power supply.
VS2 or VS3± is above its overvoltage limit.
VS1 is above its overvoltage limit.
2
C interface unless the fault is still present. It is recommended that the latched
2
C interface stays functional, but a PSON
Rev. B | Page 49 of 92
Register
0x30
0x2D
0x2D
0x5D
0x3B
0x08 to
0x0D
0x22
0x26
Register
0x34
0x30
0x0E
0x33
0x32
Action
Programmable
Programmable
Programmable
Immediate shutdown
Immediate shutdown
Programmable
Programmable
Programmable
Action
None
None
None
None
Programmable
Programmable
Programmable
ADP1046