ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 90

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

ADP1046
Table 166. Register 0x4F—OUTD Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 167. Register 0x51—SR1 Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 168. Register 0x53—SR1 Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 169. Register 0x55—SR2 Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 170. Register 0x57—SR2 Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Bit Name
Δt
time of OUTD)
Bit Name
Δt
time of SR1)
Bit Name
Δt
dead time of SR1)
Bit Name
Δt
time of SR2)
Bit Name
Δt
dead time of SR2)
8
9
10
11
12
(falling edge dead
(rising edge dead
(falling edge
(rising edge dead
(falling edge
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register sets Δt
switching cycle, t
Bit 7
0
0
…
1
Description
This register sets Δt
edge, t
Bit 7
0
0
…
1
Description
This register sets Δt
falling edge, t
Bit 7
0
0
…
1
Description
This register sets Δt
edge, t
Bit 7
0
0
…
1
Description
This register sets Δt
edge, t
Bit 7
0
0
…
1
D
E
F
. Each LSB corresponds to 5 ns of resolution.
. Each LSB corresponds to 5 ns of resolution.
. Each LSB corresponds to 5 ns of resolution.
Bit 6
0
0
…
1
Bit 6
0
0
…
1
Bit 6
0
0
…
1
Bit 6
0
0
…
1
Bit 6
0
0
…
1
E
. Each LSB corresponds to 5 ns of resolution.
Rev. B | Page 90 of 92
C
. Each LSB corresponds to 5 ns of resolution.
8
9
10
11
12
Bit 5
0
0
…
1
Bit 5
0
0
…
1
Bit 5
0
0
…
1
Bit 5
0
0
…
1
Bit 5
0
0
…
1
, which is the leading time of the falling edge of OUTD from the end of the
, which is the delay time of the rising edge of SR1 from the ACSNS rising
, which is the leading time of the falling edge of SR1 from the ACSNS
, which is the delay time of the rising edge of SR2 from the ACSNS falling
, which is the leading time of the falling edge of SR2 from the ACSNS rising
Bit 4
0
0
…
1
Bit 4
0
0
…
1
Bit 4
0
0
…
1
Bit 4
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 3
0
0
…
1
Bit 3
0
0
…
1
Bit 3
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 2
0
0
…
1
Bit 2
0
0
…
1
Bit 2
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Bit 0
0
1
…
1
Bit 0
0
1
…
1
Bit 0
0
1
…
1
Bit 0
0
1
…
1
Data Sheet
Δt
0
5
…
1275
Δt
0
5
…
1275
Δt
0
5
…
1275
Δt
0
5
…
1275
Δt
0
5
…
1275
8
9
10
11
12
(ns)
(ns)
(ns)
(ns)
(ns)