ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 16

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

ADP1046A
VOLTAGE SENSE AND CONTROL LOOP
Multiple voltage sense inputs on the
monitoring, control, and protection of the power supply output.
This information is available through the I
sense points can be calibrated digitally to minimize errors due to
external components. This calibration can be performed in the
production environment, and the settings can be stored in the
EEPROM of the
and Trim section for more information).
For voltage monitoring, the VS1, VS2, and VS3 voltage value
registers (Register 0x15, Register 0x16, and Register 0x17,
respectively) are updated every 10 ms. The
every ADC sample for 10 ms and then outputs the average value
at the end of the 10 ms period. Therefore, if these registers are
read at least every 10 ms, a true average value is read.
The
depending on the condition of the OrFET. When the OrFET is
turned off, the control loop is regulated via VS1; when the OrFET
is turned on, the control loop is regulated via the differential
sensing on VS3±. This sensing mechanism effectively performs
a local and remote voltage sense.
The control loop of the
path architecture. The output voltage is converted simultaneously
by two ADCs: a high accuracy ADC and a high speed ADC. The
complete signal is reconstructed and processed in the digital
filter to provide a high performance, cost competitive solution.
ADCs
Two kinds of Σ-Δ ADCs are used in the feedback loop of the
ADP1046A: a low frequency (LF) ADC that runs at 1.56 MHz
and a high frequency (HF) ADC that runs at 25 MHz.
Σ-Δ ADCs have a resolution of one bit and operate differently
from traditional flash ADCs. The equivalent resolution that can
be obtained depends on how long the output bit stream of the
Σ-Δ ADC is sampled.
PGND
DIGITAL
FILTER
ADP1046A
12 BITS
VS1
VS1
ADC
1V
12V
Figure 17. Voltage Sense Configuration
uses two separate sensing points: VS1 and VS3±,
11kΩ
ADP1046A
12 BITS
VS2
1kΩ
ADC
1V
12V
ADP1046A
11kΩ
VS2
12 BITS
VS3
1kΩ
(see the Power Supply Calibration
ADC
VS3
features a patented multi-
ADP1046A
ADC
HF
2
C interface. All voltage
ADP1046A
are used for the
VS3+
VS3–
stores
11kΩ
1V
1kΩ
LOAD
12V
Rev. 0 | Page 16 of 88
Σ-Δ ADCs also differ from Nyquist rate ADCs in that the quan-
tization noise is not uniform across the frequency spectrum. At
lower frequencies, the noise is lower, and at higher frequencies,
the noise is higher (see Figure 18).
The low frequency ADC runs at approximately 1.56 MHz. For a
specified bandwidth, the equivalent resolution can be calculated
as follows:
For example, at a bandwidth of 95 Hz, the equivalent
resolution/noise is
At a bandwidth of 1.5 kHz, the equivalent resolution/noise is
The high frequency ADC has a clock of 25 MHz. It is comb
filtered and outputs at the switching frequency (f
digital filter. The equivalent resolution at some sample
frequencies is listed in Table 5.
Table 5. Equivalent Resolutions for High Frequency ADC
at Various Switching Frequencies
f
48.8
97.7
195.3
390.6
The HF ADC has a range of ±30 mV. Using a base switching
frequency (f
increases to 200 kHz (7-bit HF ADC resolution), the quantization
noise is 0.9375 mV (1 LSB). Increasing f
quantization noise to 3.75 mV (1 LSB = 2 × 30 mV/2
VS1 OPERATION (VS1)
VS1 is used for the monitoring and protection of the power supply
voltage at the output of the LC stage, upstream of the OrFET. The
VS1 sense point on the power rail needs an external resistor
divider to bring the nominal input voltage to 1 V at the VS1 pin
(see Figure 17). The resistor divider is necessary because the VS1
ADC input range is 0 V to 1.6 V (12-bit reading). This divided-
down signal is internally fed into a low speed Σ-Δ ADC. The output
of the VS1 ADC goes to the digital filter and is also updated in
Register 0x15 every 10 ms. The VS1 signal is referenced to PGND.
When the OrFET is turned off, the power supply is regulated
from the VS1 sense point instead of the VS3± sense point.
SW
(kHz)
ln(1.56 MHz/BW)/ln(2) = N bits
ln(1.56 MHz/95)/ln(2) = 14 bits
ln(1.56 MHz/1.5 kHz)/ln(2) = 10 bits
Figure 18. Noise Performance for Nyquist Rate and Σ-Δ ADCs
SW
) of 100 kHz (8-bit HF ADC resolution), when f
NYQUIST ADC
NOISE
High Frequency ADC Resolution
9 bits
8 bits
7 bits
6 bits
FREQUENCY
Σ-Δ ADC
NOISE
SW
to 400 kHz increases the
Data Sheet
SW
6
= 0.9375 mV).
) into the
SW