ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 26

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

ADP1046A
Figure 35 shows the possible signals on the share bus.
The length of a bit (t
a high-to-low transition at the start of the bit and a low-to-high
transition at 75% of t
transition at the start of the bit and a low-to-high transition at
25% of t
The bus is idle when it is high during the whole period of t
All other activity on the bus is illegal. Glitches up to t
(200 ns) are ignored.
The digital word that represents the current information is eight
bits long. The
ing and uses this reading as the digital word (see Figure 36).
Digital Share Bus Scheme
Each power supply compares the digital word that it is outputting
with the digital words of all the other supplies on the bus.
PREVIOUS
LOGIC 1
LOGIC 0
IDLE
BIT
BIT
.
I
OUT
Figure 35. Share Bus High, Low, and Idle Bits
ADP1046A
= 35A
t
0
BIT
BIT
) is fixed at 10 μs. A Logic 1 is defined as
1mΩ
. A Logic 0 is defined as a high-to-low
CS2+
CS2–
takes the eight MSBs of the CS2 read-
t
1
Figure 36. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus
35mV
t
BIT
+
–
1 LSB = 29.3µV
CURRENT
SENSE
ADC
1195 DEC
12 BITS
0x4AB
GLITCH
NEXT
BIT
35mV/29.3µV = 1195
BIT
Rev. 0 | Page 26 of 88
.
DIGITAL
PSU A
FILTER
÷16
MASTER
74 DEC
8 BITS
0x4A
Round 1
In Round 1, every supply first places its MSB on the bus. If a
supply senses that its MSB is the same as the value on the bus, it
continues to Round 2. If a supply senses that its MSB is less than
the value on the bus, it means that this supply must be a slave.
When a supply becomes a slave, it stops communicating on the
share bus because it knows that it is not the master. The supply then
increases its output voltage in an attempt to share more current.
If two units have the same MSB, they both continue to Round 2
because either of them may be the master.
Round 2
In Round 2, all supplies that are still communicating on the bus
place their second MSB on the share bus. If a supply senses that
its MSB is less than the value on the bus, it means that this supply
must be a slave and it stops communicating on the share bus.
Round 3 to Round 8
The same algorithm is repeated for up to eight rounds to allow
supplies to compare their digital words and, in this way, to
determine whether each unit is the master or a slave.
Digital Share Bus Configuration
The digital share bus can be configured in various ways. The band-
width of the share bus loop is programmable in Register 0x29[2:0].
The extent to which a slave tries to match the current of the master
is programmable in Register 0x2A[3:0]. Enable the digital share
bus by setting Register 0x29[3] to 1.
DIGITAL
WORD
0x4A
0x4A
SHAREo
SHAREi
8-BIT
WORD
V
DD
SHARE
BUS
8-BIT
WORD
0xB5
Data Sheet