ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 85

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

Data Sheet
Table 150. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 151. Register 0x46—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)
Bits
[7:0]
Table 152. Register 0x47—OUTB Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Table 153. Register 0x48—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)
Bits
[7:4]
[3:0]
Bit Name
Δt
time of OUTB)
Bit Name
Highest frequency
Bit Name
Δt
time of OUTB)
Bit Name
Highest frequency
Reserved
3
4
(rising edge dead
(falling edge dead
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register sets Δt
switching cycle, t
Bit 7
0
0
…
1
Description
This register contains the eight MSBs of the 12-bit value of the highest switching frequency (mini-
mum switching cycle) limit. This value is always used with the top four bits of Register 0x48,
which contain the four LSBs of the highest switching frequency limit. Each LSB of the 12-bit
value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46
is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum
switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is
1/1.325 μs = 755 kHz. It is recommended that the maximum frequency be limited to 1 MHz.
Description
This register sets Δt
point of the switching cycle, t
value is from 0x00 to 0x7F, the falling edge of OUTB is trailing t
to 0xFF, the falling edge of OUTB is leading t
Bit 7
0
0
…
0
1
…
1
Description
This register contains the four LSBs of the 12-bit value of the highest switching frequency (mini-
mum switching cycle) limit. This value is always used with the eight bits of Register 0x46, which
contain the eight MSBs of the highest switching frequency limit. Each LSB of the 12-bit value
corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46 is set to
0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum
switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is
1/1.325 μs = 755 kHz.
Reserved.
Bit 6
0
0
…
1
Bit 6
0
0
…
1
0
…
1
Rev. 0 | Page 85 of 88
A
. Each LSB corresponds to 5 ns of resolution.
3
4
Bit 5
0
0
…
1
Bit 5
0
0
…
1
0
…
1
, which is the delay time of the rising edge of OUTB from the start of the
, which is the difference between the falling edge of OUTB and the mid-
Bit 4
0
0
…
1
B
Bit 4
0
0
…
1
0
…
1
. Each LSB corresponds to 5 ns of resolution. When the register
Bit 3
0
0
…
1
0
…
1
Bit 3
0
0
…
1
B
.
Bit 2
0
0
…
1
Bit 2
0
0
…
1
0
…
1
Bit 1
0
0
…
1
Bit 1
0
0
…
1
0
…
1
B
. When the value is from 0x80
Bit 0
0
1
…
1
0
…
1
Bit 0
0
1
…
1
Δt
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
Δt
0
5
…
1275
ADP1046A
3
4
(ns)