ADP1046ADC1-EVALZ Analog Devices, ADP1046ADC1-EVALZ Datasheet - Page 77

• Manufacturer Part Number: ADP1046ADC1-EVALZ
• Description: Power Management IC Development Tools
• Manufacturer: Analog Devices
• Type: Power Switchesr
• Series: ADP1046Ar

Specifications of ADP1046ADC1-EVALZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: ADP1046A
• Input Voltage: 36 V to 60 V
• Output Voltage: 2.5 V
• Description/function: Daughter card for ADP1046A
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• For Use With: ADP1046A

Data Sheet
Table 113. Register 0x79—SR Delay Compensation
Bits
[7:6]
[5:0]
Table 114. Register 0x7A—Filter Transitions
Bits
[7:6]
[5:3]
2
[1:0]
Table 115. Register 0x7B—PGOOD1 Flag Masking
Bits
7
6
5
4
3
2
1
0
Table 116. Register 0x7C—PGOOD2 Flag Masking
Bits
7
6
5
4
3
2
1
0
Bit Name
Reserved
SR driver delay
Bit Name
Reserved
HF ADC configuration
Enable soft transition
Transition speed
Bit Name
Soft start flag
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
UVP
Local OVP (fast and
accurate)
Load OVP
OrFET
Bit Name
Soft start flag
CS1 fast OCP
CS1 accurate OCP
CS2 accurate OCP
UVP
Local OVP (fast and
accurate)
Load OVP
OrFET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved.
These bits specify the 6-bit representation of the SR delay in steps of 5 ns.
000000 = 0 ns.
111111 = 63 ns × 5 ns = 315 ns.
Description
Reserved.
Set these bits to 001 at all times for proper operation.
Setting this bit enables a soft transition between filter settings to minimize output transients.
All four parameters of each filter are linearly transitioned to the new value.
These bits set the transition speed from one filter to another. The filter changes in 32 steps;
each step is applied at the multiple of switching cycles (t
Bit 1
0
0
1
1
Description
If this bit is set to 1, the soft start flag is ignored by PGOOD1. This bit must be set to 0 to enable
proper PGOOD1 debounce timing after the end of the soft start ramp.
If this bit is set to 1, the CS1 fast OCP flag is ignored by PGOOD1.
If this bit is set to 1, the CS1 accurate OCP flag is ignored by PGOOD1.
If this bit is set to 1, the CS2 accurate OCP flag is ignored by PGOOD1.
If this bit is set to 1, the UVP flag is ignored by PGOOD1.
If this bit is set to 1, the local OVP flag is ignored by PGOOD1.
If this bit is set to 1, the load OVP flag is ignored by PGOOD1.
If this bit is set to 1, the OrFET flag is ignored by PGOOD1.
Description
If this bit is set to 1, the soft start flag is ignored by PGOOD2. This bit must be set to 0 to enable
proper PGOOD2 debounce timing after the end of the soft start ramp.
If this bit is set to 1, the CS1 fast OCP flag is ignored by PGOOD2.
If this bit is set to 1, the CS1 accurate OCP flag is ignored by PGOOD2.
If this bit is set to 1, the CS2 accurate OCP flag is ignored by PGOOD2.
If this bit is set to 1, the UVP flag is ignored by PGOOD2.
If this bit is set to 1, the local OVP flag is ignored by PGOOD2.
If this bit is set to 1, the load OVP flag is ignored by PGOOD2.
If this bit is set to 1, the OrFET flag is ignored by PGOOD2.
Bit 0
0
1
0
1
Rev. 0 | Page 77 of 88
Speed (t
32 t
8 t
2 t
1 t
SW
SW
SW
SW
(total transition time = 8 × 32 t
(total transition time = 64 × t
(total transition time = 32 × t
(total transition time = 32 × 32 t
SW
= One Switching Cycle)
SW
) specified by these bits.
SW
SW
SW
)
)
SW
= 256 × t
= 1024 × t
SW
)
SW
)
ADP1046A