LH28F320SKTD-ZR Sharp Microelectronics, LH28F320SKTD-ZR Datasheet
LH28F320SKTD-ZR
Specifications of LH28F320SKTD-ZR
LHF32KZR
Related parts for LH28F320SKTD-ZR
LH28F320SKTD-ZR Summary of contents
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... RELIMINARY RODUCT PECIFICATION LH28F320SKTD-ZR Flash Memory (2Mbitx8/1Mbitx16 x2Bank) (Model Number: LHF32KZR) Spec. Issue Date: October 20, 2004 32Mbit Lead-free (Pb-free) Spec No: EL16X177 Integrated Circuits Group ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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INTRODUCTION ...................................................... 3 1.1 Product Overview ................................................ 3 2 PRINCIPLES OF OPERATION ................................ 7 2.1 Data Protection ................................................... 7 3 BUS OPERATION.................................................... 9 3.1 Read ................................................................... 9 3.2 Output Disable .................................................... 9 3.3 Standby ............................................................... 9 3.4 Deep Power-Down ...
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... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F320SKTD-ZR offers three levels of protection: absolute protection with V at GND, selective hardware block locking, or flexible software block locking ...
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... Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Product Overview The LH28F320SKTD- high-performance 32M- bit Smart3/5 Dual Work Flash memory organized as 2MBx8/1MBx16 x 2Bnak. The 4MB of data is arranged in sixty-four 64K-byte blocks which are individually erasable, lockable, and unlockable in- system ...
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The access time is 70ns (t ) over the commercial AVQV temperature range (0°C to +70°C) and V voltage range of 4.75V-5.25V. At lower V the access times are 80ns (4.5V-5.5V), 100ns (3.0V- 3.6V) and 120ns (2.7V-3.6V). The Automatic Power ...
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... OUTPUT DQ -DQ :Inputs data during CUI write cycles in x16 mode; outputs data during memory 8 15 array read cycles in x16 mode; not used for status register, query and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are ...
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LEAD TSOP ...
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... PRINCIPLES OF OPERATION The LH28F320SKTD-ZR Dual Work Flash memory includes an on-chip WSM to manage block erase, bank erase, (multi) word/byte write and block lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, bank erase, (multi) word/byte write and block ...
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... Block 030000 02FFFF 64K-byte Block 020000 01FFFF 64K-byte Block 010000 00FFFF 64K-byte Block 000000 Bank0 (BE #=BE #="L" Figure 3. Memory Map LHF32KZR 1FFFFF 64K-byte Block 1F0000 1EFFFF 64K-byte Block 1E0000 1DFFFF 64K-byte Block 1D0000 1CFFFF 64K-byte Block 1C0000 1BFFFF 64K-byte Block 1B0000 ...
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... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, query structure, or status register independent of the V voltage. RP# must ...
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... Block 0 Status Code 000004 000003 Device Code 000002 000001 Manufacturer Code 000000 Bank0 (BE #=BE #="L" Figure 4. Device Identifier Code Memory Map LHF32KZR 1FFFFF Future Implementation 1F0006 1F0005 Block 31 Status Code 1F0004 1F0003 Future Implementation Block 31 1F0000 1EFFFF (Blocks 2 through 30) 020000 ...
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... Lock locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location written when WE# and BE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or BE# (whichever goes high first) ...
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... ≤V , memory contents can be read, but not altered. PP PPLK or V PPLK PPH1/2/3 and CC1/2/3 and 0- OUT High High High Z High Z See V X Note 5 High Figure 4 See Table V X Note 6 High 7~ 0 OUT High High High Z High Z See V X Note 5 High Z IL ...
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... QA=Query Offset Address. BA=Address within the block being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 14 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or BE# (whichever goes high first) ...
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... Future Use NOTE selects the specific block status code to be read. See Figure 4 for the device identifier code memory map. LHF32KZR 4.3 Read Status Register Command The status register may be read to determine when a block erase, bank erase, (multi) word/byte write or block lock-bit configuration is complete and whether the operation completed successfully(see Table 14) ...
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Query Command Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 7~11 retrieve the critical information to write, erase and otherwise control the flash component ...
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CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Offset Length (Word Address) 10H,11H,12H 03H ...
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Device Geometry Definition This field provides critical details of the flash device geometry. Offset Length (Word Address) 27H 01H 28H,29H 02H 2AH,2BH 02H 2CH 01H 2DH,2EH 02H 2FH,30H 02H 4.5.5 SCS OEM Specific Extended Query Table Certain flash features ...
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Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence appropriate sequencing and an address ...
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... XSR.7. The Multi Word/Byte Write command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F320SKTD-ZR has two buffers error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded ...
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... Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written to the flash memory, the WSM will continue the (multi) word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and STS will ...
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Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V individual block lock-bits can be set using the Set Block Lock-Bit command. See ...
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STS Configuration Command The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device is ...
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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Bank Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No Suspend 0 SR.7= Word/Byte Yes Write 1 Full Status Check if Desired Word/byte Write Complete ...
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Start Write E8H, Start Address Read Extend Status Register No 0 Yes Write Buffer XSR.7= Time Out 1 Write Word or Byte Count (N)-1, Start Address Write Buffer Data, Start Address X=0 Yes Abort Buffer Write Another Write Commnad? Block ...
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FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Read Status Register 1 SR.3= V Range Error SR.1= Device Protect Error 0 1 Command Sequence SR.4,5= Error 0 1 Multi Word/Byte Write SR.4= Error 0 Multi Word/Byte ...
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Start Write B0H Read Status Register 0 SR. Block Erase Completed SR.6= 1 (Multi) Word/Byte Write Read Read or Write ? Read Array Data (Multi) Word/Byte Write Loop No Done? Yes Write FFH Write D0H Block Erase Resumed ...
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Start Write B0H Read Status Register 0 SR. (Multi) Word/Byte Write SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH (Multi) Word/Byte Write Read Array Data Resumed Figure 11. (Multi) Word/Byte ...
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Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Block Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error PP 0 ...
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Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error SR.1= Device Protect ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control accommodate multiple memory connections. Three- Line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. ...
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... V , the CUI must be placed in PPLK read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block and bank erasure, (multi) word/byte writing or block lock-bit configuration during power transitions ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration ........0°C to +70°C Temperature under Bias............... -10°C to +80°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except )............... ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
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DC CHARACTERISTICS Following is the current consumption of one bank. For the current consumption of one device total, please refer to the Note 8. Sym. Parameter Notes Typ. I Input Load Current LI I Output Leakage LO Current I ...
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Sym. Parameter Notes Min. V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage PPLK PP during Normal Operations ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t BE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t BE# ...
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Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t BE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t BE# to Output in Low Z ...
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Standby Address Selection V IH ADDRESSES( #( OE#( WE#( HIGH Z DATA(D/ PHQV V IH RP#(P) V ...
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Standby Address Selection V IH ADDRESSES( #( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH ...
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AC CHARACTERISTICS - WRITE OPERATIONS Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t BE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V Setup to ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going PHWL Low t BE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V Setup to WE# Going High SHWH IH ...
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V IH ADDRESSES( #( OE#( WE#( High Z DATA(D/ High Z STS( WP#( ...
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ALTERNATIVE BE#-CONTROLLED WRITES Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to BE# Going Low PHEL t WE# Setup to BE# Going Low WLEL t BE# Pulse Width ELEH t WP# V Setup to BE# Going ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to BE# Going Low PHEL t WE# Setup to BE# Going Low WLEL t BE# Pulse Width ELEH t WP# V Setup to BE# Going High SHEH IH ...
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V IH ADDRESSES( WE#( OE#( #( High Z DATA(D/ High Z STS( WP#( ...
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RESET OPERATIONS High Z STS( RP#( High Z STS( RP#( 2.7/3.3/ RP#( Figure 22. AC Waveform for Reset Operation ...
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BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK- BIT CONFIGURATION PERFORMANCE Sym. Parameter Word/Byte Write Time t WHQV1 (using W/B write, in word t EHQV1 mode) Word/Byte Write Time t WHQV1 (using W/B write, in byte t ...
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Sym. Parameter t Word/Byte Write Time WHQV1 t (using W/B write, in word mode) EHQV1 t Word/Byte Write Time WHQV1 t (using W/B write, in byte mode) EHQV1 Word/Byte Write Time (using multi word/byte write) Block Write Time (using W/B ...
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Sym. Parameter t Word/Byte Write Time WHQV1 t (using W/B write, in word mode) EHQV1 t Word/Byte Write Time WHQV1 t (using W/B write, in byte mode) EHQV1 Word/Byte Write Time (using multi word/byte write) Block Write Time (using W/B ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...