LH28F320SKTD-ZR Sharp Microelectronics, LH28F320SKTD-ZR Datasheet - Page 8

• Manufacturer Part Number: LH28F320SKTD-ZR
• Description: IC FLASH 32MBIT 70NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F320SKTD-ZR

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 425-2463; LHF32KZR

DQ
Symbol
BYTE#
A
BE
BE
BE
WE#
WP#
GND
RP#
OE#
STS
V
V
0
0
NC
-A
-DQ
CC
PP
1H
1L
0
#,
20
#
#
15
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY GROUND: Do not float any ground pins.
INPUT/
DRAIN
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OPEN
Type
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A
A
A
A
DATA INPUT/OUTPUTS:
DQ
array, status register, query, and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQ
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=V
BANK ENABLE: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. When BE
"low", bank1 is in active. BE
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# V
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
operation (block erase, bank erase, (multi) word/byte write or block lock-bit configuration).
STS High Z indicates that the WSM is ready for new commands, block erase is
suspended, and (multi) word/byte write is inactive, (multi) word/byte write is suspended or
the device is in deep power-down mode. For alternate configurations of the STATUS pin,
see the Configuration command.
WRITE PROTECT: Master control for block locking. When V
erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE: BYTE# V
DQ
input buffer.
BLOCK ERASE, BANK ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-BIT
CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
configuring block lock-bits. With V
erase, bank erase, (multi) word/byte write and block lock-bit configuration with an invalid
V
DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V
operation. To switch from one voltage to another, ramp V
V
the flash memory are inhibited. Device operations at invalid V
Characteristics) produce spurious results and should not be attempted.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
0
1
5
16
PP
CC
: Byte Select Address. Not used in x16 mode(can be floated).
-A
-A
0
8
0-7
-A
-DQ
-DQ
(see DC Characteristics) produce spurious results and should not be attempted.
4
15
to the new voltage. Do not float any power pins. With V
: Column Address. Selects 1 of 16 bit lines.
20
, and DQ
: Row Address. Selects 1 of 2048 word lines.
: Block Address.
7
15
:Inputs data and commands during CUI write cycles; outputs data during memory
:Inputs data during CUI write cycles in x16 mode; outputs data during memory
8-15
float. BYTE# V
Table 2. Pin Descriptions
0
# and BE
IL
IH
LHF32KZR
0
places device in x8 mode. All data is then input or output on
# and BE
enables normal operation. When driven V
1L
IL
# "low", bank0 is in active. When BE
PP
). Data is internally latched during a write cycle.
IH
Name and Function
≤V
places the device in x16 mode , and turns off the A
1L
PPLK
#, BE
, memory contents cannot be altered. Block
1H
# must not be low at the same time.
CC
CC
down to GND and then ramp
IL ,
CC
≤V
Locked blocks can not be
voltage (see DC
LKO
, all write attempts to
0
# and BE
IL
, RP# inhibits
1H
# are
0
5