LH28F320SKTD-ZR Sharp Microelectronics, LH28F320SKTD-ZR Datasheet - Page 10

• Manufacturer Part Number: LH28F320SKTD-ZR
• Description: IC FLASH 32MBIT 70NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F320SKTD-ZR

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 425-2463; LHF32KZR

2 PRINCIPLES OF OPERATION
The LH28F320SKTD-ZR Dual Work Flash memory
includes an on-chip WSM to manage block erase,
bank erase, (multi) word/byte write and block lock-bit
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, bank erase, (multi) word/byte write and block
lock-bit
overhead with RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register, query structure and identifier codes
can be accessed through the CUI independent of the
V
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration. All functions associated
with altering memory contents⎯block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration, status, query and identifier codes⎯are
accessed via the CUI and verified through the status
register.
Commands
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
bank erase, (multi) word/byte write and block lock-bit
configuration. The internal algorithms are regulated
by the WSM, including pulse repetition, internal
verification, and margining of data. Addresses and
data are internally latch during write cycles. Writing
the appropriate command outputs array data,
accesses the identifier codes, outputs query structure
or outputs status register data.
PP
voltage. High voltage on V
configuration,
are
written
and
PP
minimal
enables successful
using
processor
standard
LHF32KZR
Interface software that initiates and polls progress of
block erase, bank erase, (multi) word/byte write and
block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read or write data from any other block. Write
suspend allows system software to suspend a (multi)
word/byte write to read data from any other flash
memory array location.
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
switchable (available only when block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to V
The device accommodates either design practice and
encourages optimization of the processor-memory
interface.
When V
altered. The CUI, with multi-step block erase, bank
erase, (multi) word/byte write and block lock-bit
configuration
protection from unwanted operations even when high
voltage is applied to V
disabled when V
V
locking capability provides additional protection from
inadvertent code or data alteration by gating block
erase, bank erase and (multi) word/byte write
operations.
LKO
or when RP# is at V
PP
≤V
PPLK
command
CC
, memory contents cannot be
is below the write lockout voltage
PP
. All write functions are
sequences,
IL
. The device’s block
PP
power supply
provides
PPH1/2/3
7
.