APMOTOR56F8000E Freescale Semiconductor, APMOTOR56F8000E Datasheet - Page 100

KIT DEMO MOTOR CTRL SYSTEM

APMOTOR56F8000E

Manufacturer Part Number
APMOTOR56F8000E
Description
KIT DEMO MOTOR CTRL SYSTEM
Manufacturer
Freescale Semiconductor
Type
Motor / Motion Controllers & Driversr

Specifications of APMOTOR56F8000E

Accessory Type
Motor Controller
Input Voltage
9 V
Interface Type
RS-232
Product
Power Management Modules
For Use With/related Products
DEMO56F8013, DEMO56F8013-E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10.5 External Clock Operation Timing
10.6 Phase Locked Loop Timing
100
1. The core system clock will operate at 1/6 of the PLL output frequency.
2. This is the time required after the PLL is enabled to ensure reliable operation.
1. Parameters listed are guaranteed by design.
2. See
3. The high or low pulse width must be no smaller than 6.25ns or the chip may not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
Internal reference relaxation oscillator frequency for
the PLL
PLL output frequency
PLL lock time
Cycle to cycle jitter
Frequency of operation (external clock driver)
Clock Pulse Width
External Clock Input Rise Time
External Clock Input Fall Time
External
Note: The midpoint is V
Clock
Figure 10-4
2
Table 10-10 External Clock Operation Timing Requirements
Characteristic
Characteristic
for details on using the recommended connection of an external clock driver.
3
10%
50%
90%
1
(24 x reference frequency)
t
PW
IL
+ (V
5
4
Figure 10-4 External Clock Timing
IH
– V
IL
56F8014 Technical Data, Rev. 11
Table 10-11 PLL Timing
)/2.
2
t
PW
Symbol
f
t
t
Symbol
t
osc
PW
rise
fall
t
jitterpll
f
t
rosc
f
lock
op
6.25
Min
4
Min
t
fall
Typ
Typ
192
350
8
40
8
t
rise
Max
Freescale Semiconductor
Max
100
8
3
3
1
10%
50%
90%
MHz
V
V
Unit
MHz
MHz
Unit
ns
ns
ns
IH
IL
µs
ps

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