APMOTOR56F8000E Freescale Semiconductor, APMOTOR56F8000E Datasheet - Page 69

• Manufacturer Part Number: APMOTOR56F8000E
• Description: KIT DEMO MOTOR CTRL SYSTEM
• Manufacturer: Freescale Semiconductor
• Type: Motor / Motion Controllers & Driversr

Specifications of APMOTOR56F8000E

• Accessory Type: Motor Controller
• Input Voltage: 9 V
• Interface Type: RS-232
• Product: Power Management Modules
• For Use With/related Products: DEMO56F8013, DEMO56F8013-E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.5
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$401D.
6.3.6
This register controls the Standby mode of the large regulator. The large regulator derives the core digital
logic power supply from the IO power supply. In some circumstances, the large regulator may be put in a
reduced-power Standby mode without interfering with part operation. Refer to the overview of
power-down modes and the overview of clock generation for more information on the use of large
regulator standby.
6.3.6.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.6.2
This bit controls the pull-up resistors on the IRQA pin.
Note:
6.3.7
The CLKO select register can be used to multiplex out selected clocks generated inside the clock
generation and SIM modules. All functionality is for test purposes only and is subject to
unspecified latencies. Glitches may be produced when the clock is enabled or switched.
Freescale Semiconductor
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Base + $7
Base + $8
RESET
RESET
00 = Large regulator is in Normal mode
01 = Large regulator is in Standby (reduced-power) mode
10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset
11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset
Read
Write
Read
Write
Least Significant Half of JTAG ID (SIM_LSHID)
SIM Power Control Register (SIM_PWR)
Standby mode can be used when the device operates below 200 kHz if the PLL is shut down.
CLKO Select Register (SIM_CLKOUT)
Reserved—Bits 15–2
Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0
15
15
0
0
0
0
Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)
Figure 6-7 SIM Power Control Register (SIM_PWR)
14
14
0
0
1
1
13
13
0
0
0
0
12
0
0
12
0
0
56F8014 Technical Data, Rev. 11
11
0
0
11
0
0
10
0
0
10
0
0
9
0
0
9
0
0
8
0
0
8
0
0
7
0
0
7
0
0
6
0
0
6
0
0
5
0
0
5
0
0
4
0
0
4
1
1
3
0
0
3
1
1
2
0
0
2
1
1
Register Descriptions
1
0
LRSTDBY
1
0
0
0
0
0
1
1
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