EVAL-ADV7180LFEBZ Analog Devices Inc, EVAL-ADV7180LFEBZ Datasheet - Page 74

• Manufacturer Part Number: EVAL-ADV7180LFEBZ
• Description: BOARD EVAL FOR ADV7180 LFCSP
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7180LFEBZ

• Main Purpose: Video, SDTV Video Decoder - NTSC, PAL, SECAM
• Embedded: No
• Utilized Ic / Part: ADV7180
• Primary Attributes: CVBS (Composite), Y/C (S-video), and YPrPb (Component) Inputs
• Secondary Attributes: 8-bit ITU-R BT.656 YCrCb 4:2:2 Output
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7180
PIXEL PORT CONFIGURATION
The ADV7180 has a very flexible pixel port that can be configured
in a variety of formats to accommodate downstream ICs.
Table 100, Table 101, and Table 102 summarize the various
functions that the ADV7180 pins can have in different modes of
operation.
The ordering of components, for example, Cr vs. Cb for
Channel A, Channel B, and Channel C can be changed. See the
SWPC, Swap Pixel Cr/Cb, Address 0x27[7] section. Table 100
indicates the default positions for the Cr/Cb components.
OF_SEL[3:0], Output Format Selection, Address 0x03[5:2]
The modes in which the ADV7180 pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 102 for details.
The default LLC frequency output on the LLC pin is approximately
27 MHz. For modes that operate with a nominal data rate of
13.5 MHz (0001, 0010), the clock frequency on the LLC pin
stays at the higher rate of 27 MHz. For information on outputting
the nominal 13.5 MHz clock on the LLC pin, see the
LLC_PAD_SEL[2:0] LLC Output Selection,
Address 0x8F[6:4] section.
Table 100. 64-Lead LQFP P15 to P0 Output/Input Pin Mapping
Format and Mode
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Table 101. 48-Lead, 40-Lead, and 32-Lead Devices P7 to P0 Output/Input Pin Mapping
Format and Mode
Video Out, 8-Bit, 4:2:2
Table 102. ADV7180 Standard Definition Pixel Port Modes
OF_SEL[3:0]
0000 to 0001
0010
0011 (default)
0100 to 1111
Format
Reserved
16-bit at LLC 4:2:2
8-bit at LLC 4:2:2 (default)
Reserved
15
7
14
13
P[15:8]
YCrCb[7:0]
6
YCrCb[7:0]OUT
64-Lead LQFP P[15:0]
Y[7:0]
12
Y[7:0]OUT
Rev. F | Page 74 of 116
11
P[7:0]
5
Three-state
CrCb[7:0]
10
SWPC, Swap Pixel Cr/Cb, Address 0x27[7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
LLC_PAD_SEL[2:0] LLC Output Selection,
Address 0x8F[6:4]
The following I
(nominally at 27 MHz) and LLC (nominally at 13.5 MHz).
The LLC signal is useful for LLC-compatible wide bus (16-bit)
output modes. See the OF_SEL[3:0], Output Format Selection,
Address 0x03[5:2] section for additional information. The LLC
signal and data on the data bus are synchronized. By default, the
rising edge of LLC/LLC is aligned with the Y data; the falling
edge occurs when the data bus holds C data. The polarity of the
clock, and therefore the Y/C assignments to the clock edges, can
be altered by using the polarity LLC pin.
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC pin.
9
Data Port Pins P[15:0]
Data Port Pins P[7:0]
YCrCb[7:0]OUT
4
48-Lead LQFP, 40-Lead LFCSP, or 32-Lead LFCSP
P[7:0]
8
Reserved, do not use
Reserved, do not use
7
2
C write allows the user to select between LLC
3
6
5
YCrCb[7:0]
Not valid
2
CrCb[7:0]OUT
4
3
1
2
1
0
0