AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet
AT91SAM9G10-EK
Specifications of AT91SAM9G10-EK
Related parts for AT91SAM9G10-EK
AT91SAM9G10-EK Summary of contents
Page 1
... MHz On-chip Oscillator and two PLLs • Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals ® ® Thumb Processor ® Acceleration ® AT91 ARM Thumb-based Microcontrollers AT91SAM9G10 6462A–ATARM–03-Jun-09 ...
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... VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and for VDDPLL – 2.7V to 3.6V for VDDIOP (Peripheral I/Os) – 1.65V to 3.6V for VDDIOM (Memory I/Os) • Available in a 217-ball LFBGA RoHS-compliant Package AT91SAM9G10 2 ™ Compliant ® Infrared Modulation/Demodulation ...
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... The AT91SAM9G10 also benefits from the integration of a wide range of debug features includ- ing JTAG-ICE, a dedicated UART debug channel (DBGU). This enables the development and debug of all applications, especially those with real-time constraints. ...
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... Block Diagram Figure 2-1. AT91SAM9G10 Block Diagram JTAGSEL TDI JTAG TDO TMS Boundary Scan TCK NTRST RTCK System Controller TST AIC FIQ IRQ0-IRQ2 DRXD DBGU DTXD PDC PCK0-PCK3 PLLRCA PLLA PLLRCB PMC PLLB XIN OSC XOUT WDT PIT GPBREG XIN32 OSC ...
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... Input Input Low Input Reset/Test I/O Low Input Input Debug Unit Input Output AT91SAM9G10 Comments 1. 1.95V and 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V Do not tie over VDDBU. Accepts between 0V and VDDBU. No pull-up resistor. No pull-up resistor. ...
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... Bank Select SDWE SDRAM Write Enable RAS - CAS Row and Column Signal SDA10 SDRAM Address 10 Line MCCK Multimedia Card Clock MCCDA Multimedia Card A Command MCDA0 - MCDA3 Multimedia Card A Data AT91SAM9G10 6 Type Active Level AIC Input Input PIO I/O I/O I/O EBI I/O ...
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... Input Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter Input I/O I/O SPI I/O I/O I/O I/O Low Output Low Two-Wire Interface I/O I/O LCD Controller Output Output Output Output Output Output USB Device Port Analog Analog AT91SAM9G10 Comments 7 ...
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... Signal Description by Peripheral (Continued) Signal Name Function HDMA USB Host Port A Data - HDPA USB Host Port A Data + HDMB USB Host Port B Data - HDPB USB Host Port B Data + AT91SAM9G10 8 Type Active Level USB Host Port Analog Analog Analog Analog Comments 6462A–ATARM–03-Jun-09 ...
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... Package and Pinout The AT91SAM9G10 is available in a 217-ball LFBGA RoHS-compliant package mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9G10 Mechanical Charac- teristics” of the product datasheet. Figure 4-1. 6462A–ATARM–03-Jun-09 shows the orientation of the 217-ball LFBGA Package. ...
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... Pinout Table 4-1. AT91SAM9G10 Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 A19 D5 A2 A16/BA0 D6 A3 A14 D7 A4 A12 D10 A7 A3 D11 A8 A2 D12 A9 NC D13 A10 XOUT32 D14 A11 XIN32 D15 A12 DDP D16 A13 HDPB D17 A14 ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9G10 has six types of power supply pins: • VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to 1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal. • ...
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... This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU. AT91SAM9G10 12 6462A–ATARM–03-Jun-09 ...
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... Separate Masters for both instruction and data access providing complete AHB – Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 6462A–ATARM–03-Jun-09 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9G10 13 ...
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... Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the Multimedia Card Interface AT91SAM9G10 14 Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. ...
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... Memories Figure 8-1. AT91SAM9G10 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3/ ...
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... Slave 4 8.1 Embedded Memories • ROM – Single Cycle Access at full bus speed • Fast SRAM – Single Cycle Access at full bus speed AT91SAM9G10 16 ™ Instruction and Data), three different Slaves are Table 8-3 for details. List of Bus Matrix Masters List of Bus Matrix Slaves ...
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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9G10 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. ...
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... Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock 4. Switch the main clock to the new value. 8.2 External Memories The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3). Refer to the memory map in AT91SAM9G10 18 Figure 8-1 on page 15. 6462A–ATARM–03-Jun-09 ...
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... EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 20 Figure 8-1 on page 15 peripherals. 6462A–ATARM–03-Jun-09 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller AT91SAM9G10 19 ...
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... SLOW CLOCK XOUT32 OSC XIN MAIN OSC XOUT PLLRCA PLLA PLLRCB PLLB periph_nreset usb_suspend periph_nreset periph_clk[2..4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 AT91SAM9G10 20 System Controller irq0-irq2 Advanced fiq Interrupt Controller int MCK dbgu_irq Debug force_ntrst Unit dbgu_txd MCK Periodic debug Interval pit_irq Timer ...
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... Clock Generator Block Diagram Clock Generator XIN32 Slow Clock Oscillator XOUT32 XIN Main Oscillator XOUT PLL and PLLRCA Divider A PLL and PLLRCB Divider B Status Power Management Controller AT91SAM9G10 Slow Clock SLCK Main Clock MAINCK PLLA Clock PLLACK PLLB Clock PLLBCK Control 21 ...
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... Windowed, prevents the processor dead-lock on the watchdog access 9.9 Real-time Timer • 32-bit Free-running backup counter • Alarm Register capable to generate a wake-up of the system AT91SAM9G10 22 Power Management Controller Block Diagram Master Clock Controller SLCK Divider ...
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... Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support 6462A–ATARM–03-Jun-09 interrupts processor Generator AT91SAM9G10 23 ...
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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write AT91SAM9G10 24 peripherals 6462A–ATARM–03-Jun-09 ...
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... Note: 6462A–ATARM–03-Jun-09 Figure 8-1 on page defines the Peripheral Identifiers of the AT91SAM9G10. A peripheral identifier is Peripheral Identifiers Peripheral Mnemonic AIC SYSIRQ PIOA PIOB PIOC - US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC0 SSC1 SSC2 TC0 TC1 TC2 UHP LCDC - AIC ...
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... Peripheral Multiplexing on PIO Lines The AT91SAM9G10 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions page 30 lers. The two columns “Function” and “Comments” have been inserted for the user’s own comments ...
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... Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and/or USART0. 10.3.1.9 Interrupt Lines • Using FIQ prevents using the USART0 control signals. • Using IRQ0 prevents using the NWAIT EBI signal. • Using the IRQ1 and/or IRQ2 prevents using the SPI1. 6462A–ATARM–03-Jun-09 AT91SAM9G10 27 ...
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... TPK9 SPI1_NPCS2 PA26 TPK10 SPI1_NPCS3 PA27 TPK11 SPI0_NPCS1 PA28 TPK12 SPI0_NPCS2 PA29 TPK13 SPI0_NPCS3 PA30 TPK14 A23 PA31 TPK15 A24 AT91SAM9G10 28 Application Usage Reset Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O ...
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... I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AT91SAM9G10 Function Comments VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP ...
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... D25 TF2 PC26 D26 TK2 PC27 D27 TD2 PC28 D28 RD2 PC29 D29 RK2 PC30 D30 RF2 PC31 D31 PCK1 AT91SAM9G10 30 Application Usage Reset Comments State Power Supply I/O VDDIOM I/O VDDIOP I/O VDDIOP A25 VDDIOP I/O VDDIOP I/O VDDIOP I/O ...
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... Static Memory Controller on NCS3, Optional NAND Flash Support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support – Static Memory Controller on NCS6 - NCS7 6462A–ATARM–03-Jun-09 IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. AT91SAM9G10 31 ...
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... Automatic refresh operation, refresh rate is programmable • Energy-saving Capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not used AT91SAM9G10 32 6462A–ATARM–03-Jun-09 ...
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... By-8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding 6462A–ATARM–03-Jun-09 fifteen peripherals Sensors and data per chip select AT91SAM9G10 33 ...
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... Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.1 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used AT91SAM9G10 TDM Buses, Magnetic Card Reader and ...
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... TFT • Single clock domain architecture • Resolution supported up to 1280 x 860 6462A–ATARM–03-Jun-09 Endpoint 0: 8 bytes, no ping-pong mode Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode Endpoint 3: 64 bytes, no ping-pong mode Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode AT91SAM9G10 35 ...
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... AT91SAM9G10 36 6462A–ATARM–03-Jun-09 ...
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... The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S • a Memory Management Unit (MMU) • separate instruction and data AMBA 6462A–ATARM–03-Jun-09 ™ integer core ™ AHB bus interfaces AT91SAM9G10 ™ family of general-purpose microproces- 37 ...
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... ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. AT91SAM9G10 38 6462A–ATARM–03-Jun-09 ...
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... Table 11-1. User and System Mode R10 6462A–ATARM–03-Jun-09 shows all the registers in all modes. ™ ARM9TDMI Modes and Registers Layout Supervisor Mode Abort Mode R10 R10 AT91SAM9G10 Fast Undefined Interrupt Interrupt Mode Mode Mode R8_FIQ R9 R9 R9_FIQ R10 R10 R10_FIQ ...
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... The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC AT91SAM9G10 40 ™ ARM9TDMI Modes and Registers Layout Supervisor Mode ...
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... Undefined instruction (Undefined) • Software interrupt and Reset (Supervisor) 6462A–ATARM–03-Jun- Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than shows the status register format, where: AT91SAM9G10 Mode Mode bits Thumb state bit FIQ disable IRQ disable 41 ...
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... The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the AT91SAM9G10 42 6462A–ATARM–03-Jun-09 ...
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... Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte AT91SAM9G10 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry RSC Reverse Subtract with Carry ...
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... The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions • Exception-generating instruction AT91SAM9G10 44 ARM Instruction Mnemonic List (Continued) Operation Load Register Byte with Translation Load Register with Translation ...
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... Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch AT91SAM9G10 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry CMN Compare Negated ...
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... Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Register Notes: AT91SAM9G10 46 CP15 Registers Name ( Code (1) 0 Cache type ...
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... MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. 6462A–ATARM–03-Jun-09 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 AT91SAM9G10 CRn CRm 47 ...
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... Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). AT91SAM9G10 48 shows the different attributes of each page in the physical memory. ...
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... The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 6462A–ATARM–03-Jun-09 AT91SAM9G10 49 ...
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... This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the AT91SAM9G10 50 6462A–ATARM–03-Jun-09 ...
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... When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 6462A–ATARM–03-Jun-09 AT91SAM9G10 51 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. AT91SAM9G10 52 gives an overview of the supported transfers and different kinds of transactions they Single transfer of word, half word, or byte: • ...
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... AT91SAM9G10 Debug and Test 12.1 Overview The AT91SAM9G10 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel ...
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... Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example AT91SAM9G10 54 shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG Interface ICE/JTAG Connector RS232 AT91SAM9G10 Connector AT91SAM9G10-based Application Board Host Debugger PC Terminal 6462A–ATARM–03-Jun-09 ...
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... Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Connector AT91SAM9G10 AT91SAM9G10-based Application Board In Test Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Clock Test Data In ...
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... TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. AT91SAM9G10 56 ™ is supported via the ICE/JTAG port connected to a ...
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... The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associ- ated control signals. Each AT91SAM9G10 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad ...
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... AT91SAM9G10 58 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name NCS2 NCS3 NRD NWR0 NWR1 NWR3 SDRAMCKE SDRAMCKE/RAS/CAS SDA10/SDWE SDRAMCLK RAS CAS SDWE Pin Type ...
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... Table 12-2. Bit Number 6462A–ATARM–03-Jun-09 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 473 NCS2 472 NCS3 471 NRD 470 NWR0 469 468 NWR1 467 466 465 NWR3 464 SDRAMCKE SDRAMCKE/RAS/CAS 463 SDA10/SDWE 462 461 SDRAMCLK 460 459 RAS ...
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... AT91SAM9G10 60 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name D10 D11 D12 D13 D14 D15 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-2. Bit Number 6462A–ATARM–03-Jun-09 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 404 403 PC16 402 401 400 399 PC17 398 397 396 395 PC18 394 393 392 391 PC19 390 389 388 387 PC30 386 385 384 ...
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... AT91SAM9G10 62 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC0 PC1 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-2. Bit Number 6462A–ATARM–03-Jun-09 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 332 331 PC2 330 329 328 327 PC3 326 325 324 323 PC4 322 321 320 319 PC5 318 317 316 315 PC6 314 313 312 ...
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... AT91SAM9G10 64 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name PC11 PC12 PC13 PC14 PC15 PA0 PA1 PA2 PA3 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-2. Bit Number 6462A–ATARM–03-Jun-09 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 260 259 PA4 258 257 256 255 PA5 254 253 252 251 PA6 250 249 248 247 PA7 246 245 244 243 PA8 242 241 240 ...
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... AT91SAM9G10 66 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-2. Bit Number 6462A–ATARM–03-Jun-09 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 188 187 PA22 186 185 184 183 PA23 182 181 180 179 PA24 178 177 176 175 PA25 174 173 172 171 PA26 170 169 168 ...
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... AT91SAM9G10 68 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name PA31 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
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... Table 12-2. Bit Number 6462A–ATARM–03-Jun-09 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 116 115 PB8 114 113 112 111 PB9 110 109 108 107 PB10 106 105 104 103 PB11 102 101 100 99 PB12 PB13 PB14 PB15 86 85 ...
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... Table 12-2. Bit Number AT91SAM9G10 70 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 80 79 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 46 45 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL internal INPUT IN/OUT OUTPUT CONTROL internal INPUT IN/OUT ...
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... Table 12-2. Bit Number 6462A–ATARM–03-Jun-09 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 44 43 PB26 PB27 PB28 PB29 PB30 PB31 A[15: AT91SAM9G10 Pin Type Associated BSR Cells INPUT IN/OUT OUTPUT CONTROL internal INPUT IN/OUT OUTPUT CONTROL internal INPUT IN/OUT ...
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... Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B25 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_503F. AT91SAM9G10 72 AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name 08 A10 07 SDA10 06 A11 05 A12 ...
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... AT91SAM9G10 Boot Program 13.1 Overview The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial flash Boot program and Data- ® ...
Page 74
... Flow Diagram The Boot Program implements the algorithm in Figure 13-1. Boot Program Algorithm Flow Diagram SPI Serial Flash Boot No SPI DataFlash Boot No Nand Flash Boot AT91SAM9G10 74 Device Setup Yes Download from Serial Flash NPCS0 Timeout < Yes Download from DataFlash NPCS0 Timeout < ...
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... Initialization of the USB Device Port 6462A–ATARM–03-Jun-09 defines the crystals supported by the Boot Program. Crystals Supported by Software Auto-Detection (MHz) 3.2768 3.6864 4.608 4.9152 6.144 6.4 7.864320 8.0 12.0 12.288 16.0 17.734470 AT91SAM9G10 3.84 4.0 5.0 5.24288 6.5536 7.159090 9.8304 10.0 13.56 14.31818 18.432 20.0 75 ...
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... I==0 – P==1 – U offset added (U==1) or subtracted (U==0) – W==1 13.4.2 Structure of ARM Vector 6 The ARM exception vector 6 is used to store information needed by the DataFlash boot pro- gram. This information is described below. AT91SAM9G10 76 0x0000_0000 Internal ROM 0x0030_0000 Internal SRAM ...
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... This application may be the application code or a second-level bootloader. 6462A–ATARM–03-Jun-09 Size of the code to download in bytes ea000006 B 0x20 eafffffe B 0x04 ea00002f B _main eafffffe B 0x0c eafffffe B 0x10 <- Code size = 4660 bytes 00001234 B 0x14 eafffffe B 0x18 AT91SAM9G10 0 77 ...
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... The DataFlash boot reads the dataflash flash status register (Instruction code 0xD7). The data flash is considered as ready if bit 7 of the returned status register is set dataflash is connected does not answer, DataFlash boots exits after a 1000 attempts. AT91SAM9G10 78 Start Send status command (0x05) ...
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... LDR or Branch instruction Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91SAM9G10 No Jump to next boot solution No 79 ...
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... The SAM-BA boot principle is to: – Wait for USB Device enumeration. – In parallel, wait for character(s) received on the DBGU – Once the communication interface is identified, the application runs in an infinite AT91SAM9G10 80 loop waiting for different commands as in “Valid Image Detection” on page 76 “ ...
Page 81
... Address, NbOfBytes# go Address# display version No argument There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. : Number of bytes in hexadecimal to receive NbOfBytes AT91SAM9G10 Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# ...
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... The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. AT91SAM9G10 82 to 01) shows a transmission using this protocol. ...
Page 83
... Used to clear or disable a specific feature. Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. AT91SAM9G10 83 ...
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... MCI0 MCI0 MCI0 MCI0 TWI TWI DBGU DBGU AT91SAM9G10 84 1. Boot ROM does not support high capactiy SDCards. contains a list of pins that are driven during the boot program execution. These pins Pins Driven during Boot Program Execution Pin MOSI MISO SPCK ...
Page 85
... NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 6462A–ATARM–03-Jun-09 Reset Controller Startup Counter Reset State Manager user_reset NRST Manager nrst_out exter_nreset SLCK AT91SAM9G10 rstc_irq proc_nreset periph_nreset backup_neset 85 ...
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... This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. AT91SAM9G10 86 Figure 14-2 shows the block diagram of the NRST Manager. ...
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... VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 5-5 6462A–ATARM–03-Jun-09 XXX BMS sampling delay = 3 cycles shows how the General Reset affects the reset signals. AT91SAM9G10 ...
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... Figure 14-4. General Reset State SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9G10 88 Startup Time Processor Startup = 2 cycles XXX EXTERNAL RESET LENGTH BMS Sampling = 2 cycles Any Freq. 0x0 = General Reset XXX 6462A–ATARM–03-Jun-09 ...
Page 89
... The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 6462A–ATARM–03-Jun-09 Resynch. Processor Startup 2 cycles = 2 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) AT91SAM9G10 Any Freq. 0x1 = WakeUp Reset XXX 89 ...
Page 90
... EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these com- mands can be performed independently or simultaneously. The software reset lasts 2 Slow Clock cycles. AT91SAM9G10 Resynch ...
Page 91
... ERSTL. However, the resulting low level on NRST does not result in a User Reset state. 6462A–ATARM–03-Jun-09 Any Freq. Resynch. Processor Startup 1 cycle = 2 cycles XXX Any EXTERNAL RESET LENGTH AT91SAM9G10 0x3 = Software Reset 8 cycles (ERSTL=2) 91 ...
Page 92
... A watchdog event is impossible because the Watchdog Timer is being reset by the – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. AT91SAM9G10 92 Any Freq. Processor Startup ...
Page 93
... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 6462A–ATARM–03-Jun-09 AT91SAM9G10 read RSTC_SR 2 cycle resynchronization Figure 93 ...
Page 94
... Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. AT91SAM9G10 94 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset Back-up Reset ...
Page 95
... If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6462A–ATARM–03-Jun- KEY – – – – – – – – EXTRST AT91SAM9G10 – – – PERRST – PROCRST 24 16 – 8 – ...
Page 96
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. AT91SAM9G10 – ...
Page 97
... KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6462A–ATARM–03-Jun- KEY – – – – – URSTIEN – AT91SAM9G10 – – ERSTL – – URSTEN (ERSTL+1) Slow Clock cycles. This 97 ...
Page 98
... AT91SAM9G10 98 6462A–ATARM–03-Jun-09 ...
Page 99
... Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 6462A–ATARM–03-Jun-09 set 0 RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV AT91SAM9G10 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 99 ...
Page 100
... Figure 15-2. RTT Counting RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9G10 100 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 101
... Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6462A–ATARM–03-Jun-09 AT91SAM9G10 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 ...
Page 102
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9G10 102 – ...
Page 103
... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time Timer Value Register Register Name: RTT_VR Address: 0xFFFFFD28 Access Type: Read-only • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6462A–ATARM–03-Jun- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV AT91SAM9G10 103 ...
Page 104
... The Real-time Alarm occured since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9G10 104 – ...
Page 105
... Periodic Interval Counter, PICNT. The status bit PITS in the Status Regis- ter (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). 6462A–ATARM–03-Jun-09 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91SAM9G10 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR ...
Page 106
... PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface AT91SAM9G10 106 APB cycle MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR Figure 16-2 APB cycle ...
Page 107
... Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register 6462A–ATARM–03-Jun-09 AT91SAM9G10 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset 0x000F_FFFF 0x0000_0000 ...
Page 108
... PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. AT91SAM9G10 108 – ...
Page 109
... Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. 6462A–ATARM–03-Jun- – – – – – – – – – – – – PICNT CPIV CPIV AT91SAM9G10 – – – – – – – – – – – PITS CPIV 109 ...
Page 110
... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. 6462A–ATARM–03-Jun- PICNT CPIV CPIV AT91SAM9G10 CPIV 110 ...
Page 111
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6462A–ATARM–03-Jun-09 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset AT91SAM9G10 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 111 ...
Page 112
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM9G10 112 6462A–ATARM–03-Jun-09 ...
Page 113
... Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9G10 113 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6462A–ATARM–03-Jun-09 ...
Page 114
... Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9G10 114 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6462A–ATARM–03-Jun-09 ...
Page 115
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9G10 115 KEY – – – – – ...
Page 116
... The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. AT91SAM9G10 116 ...
Page 117
... WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9G10 117 6462A–ATARM–03-Jun-09 ...
Page 118
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM9G10 118 – ...
Page 119
... The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Con- troller has no effect on the behavior of the Shutdown Controller. 6462A–ATARM–03-Jun-09 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset RTTWK SHDW_MR SHDW_SR set AT91SAM9G10 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW Type Input Output 119 ...
Page 120
... SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails. AT91SAM9G10 120 SHDN ...
Page 121
... Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6462A–ATARM–03-Jun-09 AT91SAM9G10 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0303 0x0000_0000 121 ...
Page 122
... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9G10 122 KEY – – – – – ...
Page 123
... Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change SHDN pin. AT91SAM9G10 26 25 – – – – – – – – – – WKMODE0 SHDN pin is released 24 – ...
Page 124
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTTWK: Real-time Timer Wake- wake-up alarm from the RTT occurred since the last read of SHDW_SR least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. AT91SAM9G10 124 – ...
Page 125
... The System Controller embeds Four general-purpose backup registers. 19.1.1 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0xC General Purpose Backup Register 3 6462A–ATARM–03-Jun-09 AT91SAM9G10 Name SYS_GPBR0 ... SYS_GPBR3 Access Reset Read-write – ... ... Read-write – 125 ...
Page 126
... General Purpose Backup Register x Register Name: SYS_GPBRx Addresses: 0xFFFFFD50 [0], 0xFFFFFD54 [1], 0xFFFFFD58 [2], 0xFFFFFD5C [3] Access Type: Read-write • GPBR_VALUEx: Value of GPBR x AT91SAM9G10 126 GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx 6462A–ATARM–03-Jun-09 ...
Page 127
... DEFMSTR_TYPE flag selects the default master type (no default, last access master, fixed default master) whereas the 3-bit FIXED_DEFMSTR flag selects a fixed default master provided that DEFMSTR_TYPE is set to a fixed default master. See face” on page 6462A–ATARM–03-Jun-09 129. AT91SAM9G10 “Bus Matrix (MATRIX) User Inter- 127 ...
Page 128
... Any request attempted by this fixed default master does not cause any latency, whereas other non-privileged masters still obtain one latency cycle. This technique can be used for masters that perform mainly single accesses. AT91SAM9G10 128 6462A–ATARM–03-Jun-09 ...
Page 129
... Slave Configuration Register 2 0x0010 Slave Configuration Register 3 0x0014 Slave Configuration Register 4 0x0018 - 0x002C Reserved 0x0030 EBI Chip Select Assignment Register 0x0034 USB Pad Pull-up Control Register 6462A–ATARM–03-Jun-09 AT91SAM9G10 Name Access MATRIX_MCFG Write only MATRIX_SCFG0 Read-write MATRIX_SCFG1 Read-write MATRIX_SCFG2 Read-write MATRIX_SCFG3 ...
Page 130
... RCBx: Remap Command Bit for AHB Master effect 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x. AT91SAM9G10 130 – – – – – – ...
Page 131
... This results in not having the one cycle latency when the fixed master is trying to access the slave again. • FIXED_DEFMSTR: Fixed Index of Default Master This is the index of the Fixed Default Master for this slave. 6462A–ATARM–03-Jun- – – – FIXED_DEFMSTR – – – SLOT_CYCLE AT91SAM9G10 – – – DEFMSTR_TYPE – – – 131 ...
Page 132
... EBI Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. • EBI_DBPUC: EBI Data Bus Pull-Up Configuration 0 = EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM power supply EBI D0 - D15 Data Bus bits are not internally pulled-up. AT91SAM9G10 132 – ...
Page 133
... UDP_PUP_ON: UDP Pad Pull-up Enable 0: Pad pull-up disabled 1: Pad pull-up enabled 6462A–ATARM–03-Jun- – – – – – – – – – – – – AT91SAM9G10 – – – – – – – – – – – – 133 ...
Page 134
... AT91SAM9G10 134 6462A–ATARM–03-Jun-09 ...
Page 135
... Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus bits eight chip select lines (NCS[7:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 6462A–ATARM–03-Jun-09 AT91SAM9G10 135 ...
Page 136
... Block Diagram Figure 21-1 Figure 21-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9G10 136 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Logic Static Memory Controller NAND Flash Logic CompactFlash Logic ...
Page 137
... NWR0 - NWR3 Write Signals NBS0 - NBS3 Byte Mask Signals SDA10 SDRAM Address 10 Line 6462A–ATARM–03-Jun-09 EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller AT91SAM9G10 Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 138
... A2 - A25 A[2:25] NCS0 CS NCS1/SDCS CS NCS2 CS NCS3/NANDCS CS NCS4/CFCS0 CS AT91SAM9G10 138 details the connections between the two Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections EBI Pins SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported ...
Page 139
... D16 - D31 – DQM0 A0 DQM2 A1 A[0:8] A[2:10] A9 – A10 – – – A[11:12] – – – BA0 – BA1 – – – – – – REG AT91SAM9G10 4 x 8-bit 2 x 16-bit 32-bit Static Static Static Devices Devices ( (2) (3) WE NUB (2) (4) WE NUB Compact ...
Page 140
... CE connection depends on the NAND Flash. For standard NAND Flash devices, it must be connected to any free PIO line. For “CE don’t care” NAND Flash devices, it can be connected to either NCS3/NANDCS or to any free PIO line. AT91SAM9G10 140 Pins of the Interfaced Device ...
Page 141
... RAS BA0 A17/BA1 CAS BA1 DQM NBS2 128K x 8 SRAM A1-A17 D0-D7 A0-A16 D0-D7 D8-D15 CS OE NRD/NOE NRD/NOE WE A0/NWR0/NBS0 NWR1/NBS1 AT91SAM9G10 SDRAM D8-D15 D0-D7 CS CLK A0-A9, A11 A2-A11, A13 CKE SDWE A10 SDA10 WE BA0 A16/BA0 RAS BA1 A17/BA1 CAS DQM NBS1 ...
Page 142
... NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. AT91SAM9G10 142 6462A–ATARM–03-Jun-09 ...
Page 143
... Offset 0x0040 0000 Offset 0x0000 0000 The A22 pin of the EBI is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). CompactFlash Mode Selection AT91SAM9G10 True IDE Alternate Mode Space True IDE Mode Space I/O Mode Space Common Memory Mode Space ...
Page 144
... CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. 21-4 on page 145 Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values. AT91SAM9G10 144 CFCE1 DBW ...
Page 145
... A21 A20 NRD NWR0_NWE CFOE CFWE NRD NWR0_NWE and Table 21-9 on page 146 Table 21-9 on page 146 remain shared between all memory areas when the cor- CompactFlash Signals CS5A = 1 CFCS1 AT91SAM9G10 CompactFlash Logic CFOE 1 1 CFWE 1 0 CFIOR 1 CFIOW 1 1 CFIOR ...
Page 146
... The CompactFlash _WAIT sig- nal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller section. AT91SAM9G10 146 Access to CompactFlash Device CompactFlash Signals ...
Page 147
... NCS6 and NCS7 (i.e., between 0x70000000 and 0x8FFF FFFF) may lead to an unpredictable outcome. 6462A–ATARM–03-Jun-09 EBI D[15:0] A25/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NRD/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW CFCE1 CFCE2 NWAIT AT91SAM9G10 CompactFlash Connector D[15:0] DIR /OE _CD1 _CD2 /OE A[10:0] _REG _OE _WE _IORD _IOWR _CE1 _CE2 _WAIT ...
Page 148
... NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B) sig- nals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not selected, preventing the device from returning to standby mode. AT91SAM9G10 148 MUX Logic CS3A ...
Page 149
... Figure 21-7. NAND Flash Application Example Note: 6462A–ATARM–03-Jun-09 D[7:0] A[22:21] NCS3/NANDCS EBI NCS6/NANDOE NCS7/NANDWE PIO PIO The External Bus Interface is also able to support 16-bits devices. AT91SAM9G10 AD[7:0] ALE CLE Not Connected NAND Flash NOE NWE CE R/B 149 ...
Page 150
... Select Assignment Register located in the bus matrix memory space. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM device initialisation” part of the SDRAM controller. AT91SAM9G10 150 ...
Page 151
... C4 100NF VDDQ 100NF C5 100NF CLK VDDQ 43 C6 100NF C6 100NF VDDQ 100NF C7 100NF DQML VDDQ 39 DQMH 28 VSS 17 41 CAS VSS 18 54 RAS VSS 6 VSSQ 12 VSSQ VSSQ VSSQ 256 Mbits TSOP54 PACKAGE AT91SAM9G10 DQ0 MT48LC16M16A2 MT48LC16M16A2 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ...
Page 152
... PIO controller. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. AT91SAM9G10 152 U1 U1 ...
Page 153
... 3V3 10K 10K 1 N.C 2 N.C 3 N.C 4 N.C 5 N.C 6 N.C 10 N.C 11 N.C 14 N.C 15 N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 N.C 34 N TSOP48 PACKAGE AT91SAM9G10 I/O9 D10 31 I/O10 D11 33 I/O11 D12 41 I/O12 D13 43 I/O13 D14 45 I/O14 D15 ...
Page 154
... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. AT91SAM9G10 154 D[0..15] A[1..22] ...
Page 155
... SN74ALVC125 10K 10K RDY/BSY 11 12 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K WAIT GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9G10 MEMORY & I/O MODE 3V3 J1 J1 CF_D15 31 38 D15 VCC CF_D14 30 D14 CF_D13 29 13 D13 VCC CF_D12 28 D12 CF_D11 27 D11 CF_D10 ...
Page 156
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9G10 156 6462A–ATARM–03-Jun-09 ...
Page 157
... SN74ALVC125 10K 10K INTRQ 11 12 3V3 MN4 MN4 5 1 3V3 VCC VCC R4 R4 10K 10K IORDY 4 2 3V3 3 GND GND SN74LVC1G125-Q1 SN74LVC1G125-Q1 AT91SAM9G10 TRUE IDE MODE 3V3 J1 J1 CF_D15 D15 VCC CF_D14 100NF 100NF 30 D14 CF_D13 D13 VCC CF_D12 100NF 100NF ...
Page 158
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. AT91SAM9G10 158 6462A–ATARM–03-Jun-09 ...
Page 159
... Write or Byte Select Access” on page 161 8-/16-bit or 32-bit data bus, see “Data Bus Width” on page Byte-write or byte-select access, see Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 161 AT91SAM9G10 Type Output Output Output Output Output ...
Page 160
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. AT91SAM9G10 160 128K x 8 SRAM ...
Page 161
... This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6462A–ATARM–03-Jun-09 NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2. Figure 22-5 AT91SAM9G10 Figure 22-2). NCS7 Memory Enable NCS6 Memory Enable NCS5 Memory Enable ...
Page 162
... Figure 22-3. Memory Connection for an 8-bit Data Bus Figure 22-4. Memory Connection for a 16-bit Data Bus Figure 22-5. Memory Connection for a 32-bit Data Bus SMC AT91SAM9G10 162 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] ...
Page 163
... Byte Select Access is used to connect two 16-bit devices. Figure 22-7 mode, on NCS3 (BAT = Byte Select Access). 6462A–ATARM–03-Jun-09 Figure 22-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access AT91SAM9G10 163 ...
Page 164
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91SAM9G10 164 D[7:0] D[15:8] ...
Page 165
... Byte Select Byte Write NBS0 NWE NWR0 NBS1 NWR1 NBS2 NWR2 NBS3 NWR3 AT91SAM9G10 D[15:0] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable ...
Page 166
... NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. AT91SAM9G10 166 Figure 22-8. NRD_SETUP NRD_PULSE ...
Page 167
... NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 22.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 22-9). 167 ...
Page 168
... NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro- grammed waveform of NCS may be. AT91SAM9G10 168 NRD_PULSE NRD_PULSE ...
Page 169
... Figure 22-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 6462A–ATARM–03-Jun-09 t PACC Data Sampling shows the typical read cycle of an LCD module. The read data is valid t t PACC Data Sampling AT91SAM9G10 after PACC 169 ...
Page 170
... NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 22-12. Write Cycle MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NCS_WR_SETUP AT91SAM9G10 170 NWE_SETUP NWE_PULSE NCS_WR_PULSE NWE_CYCLE Figure 22-12. The write cycle NWE_HOLD NCS_WR_HOLD 6462A–ATARM–03-Jun-09 ...
Page 171
... NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 22.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null value leads to unpredictable behavior. 6462A–ATARM–03-Jun-09 NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE AT91SAM9G10 Figure 22-13). How- NWE_PULSE NCS_WR_PULSE NWE_CYCLE 171 ...
Page 172
... NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. AT91SAM9G10 172 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is shows the waveforms of a write operation with WRITE_MODE set to 0. The data is 6462A– ...
Page 173
... Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] AT91SAM9G10 Permitted Range Coded Value Effective Value 0 ≤ ≤ ≤ ≤ 128+31 0 ≤ ≤ ≤ ≤ 256+63 0 ≤ ...
Page 174
... During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 22-16 Select 2. AT91SAM9G10 174 gives the default value of timing parameters at reset. Reset Values of Timing Parameters Reset Value ...
Page 175
... If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See 6462A–ATARM–03-Jun-09 NRD_CYCLE Read to Write Wait State (Figure 22-17). Figure AT91SAM9G10 NWE_CYCLE Chip Select Wait State 22-19. (Figure 175 ...
Page 176
... Figure 22-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD D[31:0] AT91SAM9G10 176 no hold write cycle Early Read wait state no hold write cycle Early Read ...
Page 177
... Cycle, Mode) if accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while fetching the code from a memory connected on this CS, may lead 6462A–ATARM–03-Jun-09 MCK no hold NRD write cycle Early Read (WRITE_MODE = 1) wait state AT91SAM9G10 read setup = 1 read cycle (READ_MODE = 0 or READ_MODE = 1) 177 ...
Page 178
... SMC accesses. This wait cycle is referred read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See AT91SAM9G10 178 “Slow Clock Mode” on page Figure 22-16 on page 175 ...
Page 179
... NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. 6462A–ATARM–03-Jun-09 ) for each external memory device is programmed in the DF will not slow down the execution of a program from internal DF illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), AT91SAM9G10 Figure 22-21 shows the read oper- 179 ...
Page 180
... D[31:0] Figure 22-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS D[31:0] AT91SAM9G10 180 tpacc TDF = 2 clock cycles NRD controlled read operation tpacc TDF = 3 clock cycles NCS controlled read operation 6462A–ATARM–03-Jun-09 ...
Page 181
... TDF optimization. 6462A–ATARM–03-Jun-09 shows a read access controlled by NRD, followed by a write access controlled by NRD_HOLD= 4 TDF_CYCLES = 6 Read to Write Wait State 22-23, Figure 22-24 and Figure 22-25 AT91SAM9G10 NWE_SETUP= 3 write access on NCS0 (NWE controlled) illustrate the cases: 181 ...
Page 182
... NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] read1 cycle TDF_CYCLES = 4 AT91SAM9G10 182 read1 hold = 1 TDF_CYCLES = 6 5 TDF WAIT STATES Chip Select Wait State read1 hold = 1 TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select ...
Page 183
... The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 6462A–ATARM–03-Jun-09 read1 hold = 1 TDF_CYCLES = 5 read1 cycle Read to Write Wait State (“Asynchronous Page Mode” on page 189). AT91SAM9G10 write2 setup = 1 4 TDF WAIT STATES write2 cycle TDF_MODE = 0 (optimization disabled) 192 Slow Clock Mode 183 ...
Page 184
... The assertion of the NWAIT signal outside the expected period is ignored as illustrated in 22-27. Figure 22-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal AT91SAM9G10 184 FROZEN STATE Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 1 ...
Page 185
... Figure 22-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6462A–ATARM–03-Jun-09 FROZEN STATE Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 AT91SAM9G10 Assertion is ignored 0 0 185 ...
Page 186
... Figure 22-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 5 NCS D[31:0] NWAIT internally synchronized NWAIT signal 6462A–ATARM–03-Jun- Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 AT91SAM9G10 Figure 22-28 and Figure 22-29. After Wait STATE Fig- 186 ...
Page 187
... Figure 22-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6462A–ATARM–03-Jun- Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 AT91SAM9G10 Wait STATE Assertion is ignored 187 ...
Page 188
... NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 22-30. NWAIT Latency MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWAIT intenally synchronized NWAIT signal 6462A–ATARM–03-Jun- minimal pulse length NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 AT91SAM9G10 WAIT STATE Fig- 188 ...
Page 189
... They are valid on all Table 22-6 indicates the value of read and write parameters in slow clock mode Read and Write Timing Parameters in Slow Clock Mode Duration (cycles AT91SAM9G10 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD 1 1 NCS NRD_CYCLE = 2 SLOW CLOCK MODE READ ...
Page 190
... This write cycle finishes with the slow clock mode set of parameters after the clock rate transition 6462A–ATARM–03-Jun-09 illustrates the recommended procedure to properly switch from one mode to the NWE_CYCLE = 3 SLOW CLOCK MODE WRITE AT91SAM9G10 NWE_CYCLE = 7 NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State ...
Page 191
... Figure 22-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK MODE WRITE 6462A–ATARM–03-Jun- IDLE STATE AT91SAM9G10 NORMAL MODE WRITE Reload Configuration Wait State 191 ...
Page 192
... A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored. shows the NRD and NCS timings in page mode access. tpa NRD_PULSE NCS_RD_PULSE AT91SAM9G10 Table 22-7. ) takes longer than the subse- pa Figure 22-34 ...
Page 193
... Access time of subsequent accesses in the page sa ‘x’ No impact ) and the NRD_PULSE for accesses to the page ( shorter than the programmed value for Figure 22- AT91SAM9G10 Table 22- Table 22-7 are identical, then the cur- illustrates access to an 8-bit memory device in ), even if sa 193 ...
Page 194
... Figure 22-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6462A–ATARM–03-Jun-09 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91SAM9G10 NRD_PULSE 194 ...
Page 195
... Reserved 6462A–ATARM–03-Jun-09 Table 22-9. For each chip select, a set of 4 registers is used to pro- Table 22-9, “CS_number” denotes the chip select number. Name Access SMC_SETUP Read-write SMC_PULSE Read-write SMC_CYCLE Read-write SMC_MODE Read-write - AT91SAM9G10 Reset 0 0x01010101 0x00010001 0x10001000 - - 195 ...
Page 196
... The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles • NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 6462A–ATARM–03-Jun- NCS_RD_SETUP NCS_WR_SETUP AT91SAM9G10 NRD_SETUP NWE_SETUP 196 ...
Page 197
... NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. 6462A–ATARM–03-Jun- NCS_RD_PULSE NRD_PULSE NCS_WR_PULSE NWE_PULSE AT91SAM9G10 197 ...
Page 198
... The total read cycle length is the total duration in clock cycles of the read cycle equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles 6462A–ATARM–03-Jun- – – – NRD_CYCLE – – – NWE_CYCLE AT91SAM9G10 – – NRD_CYCLE – – NWE_CYCLE 198 ...
Page 199
... Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. 6462A–ATARM–03-Jun- – – TDF_MODE DBW – EXNW_MODE – NWAIT Mode 0 Disabled 1 Reserved 0 Frozen Mode 1 Ready Mode AT91SAM9G10 – – PMEN TDF_CYCLES – – BAT – WRITE_MODE READ_MODE 199 ...
Page 200
... Standard read is applied. • PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes 6462A–ATARM–03-Jun-09 Data Bus Width 0 8-bit bus 1 16-bit bus 0 32-bit bus 1 Reserved Page Size 0 4-byte page 1 8-byte page 0 16-byte page 1 32-byte page AT91SAM9G10 200 ...