AT91SAM9G10-EK Atmel, AT91SAM9G10-EK Datasheet - Page 127

• Manufacturer Part Number: AT91SAM9G10-EK
• Description: KIT DEV FOR SAM9G10 ARM
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G10-EK

• Contents: Board, Cables, Power Supply
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9G10, ARM926EJ-S
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

20. Bus Matrix (MATRIX)
20.1
20.2
20.3
20.3.1
20.3.2
20.3.3
6462A–ATARM–03-Jun-09
Description
Memory Mapping
Special Bus Granting Techniques
No Default Master
Last Access Master
Fixed Default Master
The Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel
access paths between multiple AHB masters and slaves in a system, thus increasing the overall
bandwidth. The Bus Matrix interconnects 5 AHB Masters to 5 AHB Slaves. The Bus Matrix user
interface is compliant with the ARM Advanced Peripheral Bus and provides 5 Special Function
Registers (MATRIX_SFR) that allow the Bus Matrix to support application-specific features.
The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each
AHB Master several memory mappings. Depending on the product, each memory area may be
assigned to several slaves. Booting at the same address while using different AHB slaves (i.e.,
external RAM, internal ROM, internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides a Master Configuration Register (MATRIX_MCFG) that
performs a remap action for every master independently.
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This technique reduces latency at first accesses. The bus granting
technique sets a default master for every slave. At the end of the current access, if no other
request is pending, the slave remains connected to its associated default master. A slave can be
associated with three kinds of default masters; no default master, last access master and fixed
default master.
At the end of current access, if no other request is pending, the slave is disconnected from all
masters. No Default Master suits low-power mode.
At the end of current access, if no other request is pending, the slave remains connected to the
last master that performs an access request.
At the end of current access, if no other request is pending, the slave remains connected to its
fixed default master. Unlike last access master, the fixed master does not change unless the
user changes it by a software action.
To change from one kind of default master to another, the Bus Matrix user interface provides 5
Slave Configuration Registers, one for each slave, that set default master for each slave. The
Slave Configuration Register contains two fields; DEFMSTR_TYPE and FIXED_DEFMSTR. The
2-bit DEFMSTR_TYPE flag selects the default master type (no default, last access master, fixed
default master) whereas the 3-bit FIXED_DEFMSTR flag selects a fixed default master provided
that DEFMSTR_TYPE is set to a fixed default master. See
face” on page
129.
“Bus Matrix (MATRIX) User Inter-
AT91SAM9G10
127