C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 147
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C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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15.5. FIFO Management
1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between
Endpoints0-3 as shown in Figure 15.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT,
or both (Split Mode: half IN, half OUT).
15.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured
for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes
(0x0440 to 0x053F) are used by Endpoint3 OUT.
If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to
form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see Figure 15.20).
0x07C0
0x07BF
0x07FF
0x073F
0x063F
0x043F
0x03FF
0x0740
0x0640
0x0440
0x0400
0x0000
(1024 bytes)
User XRAM
(128 bytes)
(256 bytes)
(512 bytes)
Figure 15.3. USB FIFO Allocation
Endpoint0
Endpoint1
Endpoint2
Endpoint3
(64 bytes)
(64 bytes)
Free
Rev. 1.4
USB Clock Domain
System Clock Domain
IN, OUT, or both (Split
Configurable as
Mode)
C8051F320/1
147
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